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Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHN1018
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
d
= 25 V
DSS
• Low on-state resistance
• Fast switching I
= 9.6 A
D
• Low-profile surface mount
package R
g
≤ 18 mΩ (VGS = 10 V)
DS(ON)
• Logic level compatible
s
R
≤ 21 mΩ (VGS = 5 V)
DS(ON)
GENERAL DESCRIPTION PINNING SOT96-1 (SO8)
N-channel enhancement mode PIN DESCRIPTION
logic level field-effect power
transistor in a surface mounting 1-3 source
plastic package using ’trench’
technology. 4 gate
Application:- 5-8 drain
• High frequency computer
motherboard d.c. to d.c. converters
pin 1 index
1234
The PHN1018 is supplied in the
SOT96-1 (SO8) surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
5678
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
V
DGR
Drain-source voltage Tj = 25 ˚C to 150˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 150˚C; - 25 V
RGS = 20 kΩ
V
GS
V
GSM
Gate-source voltage (DC) - - ± 15 V
Gate-source voltage (pulse peak - ± 20 V
value)
I
D
Drain current (tp ≤ 10 s) Ta = 25 ˚C - 9.6 A
Ta = 70 ˚C - 7.7 A
I
DM
P
tot
Drain current (pulse peak value) Ta = 25 ˚C - 38 A
Total power dissipation Ta = 25 ˚C - 2.5 W
Ta = 70 ˚C - 1.6 W
Tj, T
stg
Operating junction and storage - - 55 150 ˚C
temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-a
R
th j-a
Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec - 50 K/W
to ambient
Thermal resistance junction Surface mounted, FR4 board 150 - K/W
to ambient
October 1999 1 Rev 1.200
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Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHN1018
Logic level FET
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 150˚C 0.6 - - V
Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 10 A - 13 18 mΩ
resistance VGS = 5 V; ID = 10 A - 18 21 mΩ
VGS = 5 V; ID = 10 A; Tj = 150˚C - - 36 mΩ
Forward transconductance VDS = 25 V; ID = 10 A 8 25 - S
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 150˚C - - 500 µA
Total gate charge ID = 10 A; V
= 15 V; VGS = 5 V - 17 - nC
DD
Gate-source charge - 4 - nC
Gate-drain (Miller) charge - 6 - nC
Turn-on delay time VDD = 15 V; ID = 25 A; - 6.4 12 ns
Turn-on rise time VGS = 10 V; RG = 5 Ω -6275ns
Turn-off delay time Resistive load - 50 75 ns
Turn-off fall time - 30 45 ns
Internal drain inductance Drain leads to centre of die - 1 - nH
Internal source inductance Source leads to source bond pad - 3 - nH
Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 1050 - pF
Output capacitance - 330 - pF
Feedback capacitance - 220 - pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
SD
t
rr
Q
rr
October 1999 2 Rev 1.200
Continuous source current Ta = 25 ˚C, tp ≤ 10 s - - 9.6 A
(body diode)
Pulsed source current (body - - 38 A
diode)
Diode forward voltage IF = 10 A; VGS = 0 V - 0.83 1.2 V
Reverse recovery time IF = 10 A; -dIF/dt = 100 A/µs; - 100 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 0.13 - µC
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Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHN1018
Logic level FET
Normalised Power Derating, Ptot (%)
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160
Ambient temperature, Ta (C)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
Normalised Current Derating, ID (%)
120
100
80
60
40
20
0
0 20 40 60 80 100 120 140 160
Ambient temperature, Ta (C)
D 25 ˚C
= f(Ta)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Ta); conditions: VGS ≥ 5 V
D 25 ˚C
Transient thermal impedance, Zth j-mb (K/W)
100
D = 0.5
0.2
10
0.1
0.05
0.02
1
P
single pulse
0.1
0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
D
D = tp/T
tp
T
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-a
Drain Current, ID (A)
50
45
40
35
30
25
20
15
10
5
0
VGS = 10 V
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
5 V
4.5 V
Drain-Source Voltage, VDS (V)
Tj = 25 C
3.2 V
3 V
2.8 V
2.6 V
2.4 V
2.2 V
Fig.5. Typical output characteristics, Tj = 25 ˚C
ID = f(VDS); parameter V
GS
.
Peak Pulsed Drain Current, IDM (A)
100
RDS(on) = VDS/ ID
10
1
0.1
0.01
0.1 1 10 100
D.C.
Drain-Source Voltage, VDS (V)
tp = 10 us
100 us
1 ms
10 ms
100 ms
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
p
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.2 V
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0 5 10 15 20 25 30 35 40 45 50
2.4 V
2.6 V
2.8V
3 V
Drain Current, ID (A)
3.2 V
5 V
Tj = 25 C
VGS =4.5 V
10V
Fig.6. Typical on-state resistance, Tj = 25 ˚C
R
= f(ID); parameter V
DS(ON)
GS
.
October 1999 3 Rev 1.200