Philips PHK4NQ20T User Manual

PHK4NQ20T

TrenchMOS™ standard level FET

M3D315	Rev. 01 — 20 January 2003	Product data

1.Product profile

1.1Description

N-channel enhancement mode field-effect transistor in a plastic package using

TrenchMOS™ technology.

Product availability:

PHK4NQ20T in SOT96-1 (SO8).

1.2Features

■Low on-state resistance

■Surface mount package.

1.3Applications

■DC-DC primary side switching

■General purpose switch.

1.4Quick reference data

■ VDS ≤ 200 V

■ ID ≤ 4 A

■ Ptot ≤ 6.25 W

■ RDSon ≤ 130 mΩ

2. Pinning information

Table 1: Pinning - SOT96-1, simplified outline and symbol

Pin

Description

Simplified outline

Symbol

1,2,3

source (s)

8

5

d

4

gate (g)

5,6,7,8

drain (d)

g

1

4

Top view

MBK187

MBB076 s

SOT96-1

Philips Semiconductors	PHK4NQ20T
	TrenchMOS™ standard level FET

3. Limiting values

Table 2: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol	Parameter	Conditions		Min	Max	Unit
VDS	drain-source voltage (DC)	25 °C ≤ Tj ≤ 150 °C		-	200	V
VDGR	drain-gate voltage (DC)	25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ		-	200	V
VGS	gate-source voltage (DC)			-	±20	V
ID	drain current (DC)	Tsp = 25 °C; VGS = 10 V; Figure 2 and 3		-	4	A
		Tsp = 100 °C; VGS = 10 V; Figure 2		-	2.58	A
IDM	peak drain current	Tsp = 25	°C; pulsed; tp ≤ 10 μs; Figure 3	-	16	A
Ptot	total power dissipation	Tsp = 25	°C; Figure 1	-	6.25	W
Tstg	storage temperature			−55	+150	°C
Tj	junction temperature			−55	+150	°C
Source-drain diode
IS	source (diode forward) current (DC)	Tsp = 25	°C	-	4	A
ISM	peak source (diode forward) current	Tsp = 25	°C; pulsed; tp ≤ 10 μs	-	16	A

9397 750 10773

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 20 January 2003

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Philips Semiconductors	PHK4NQ20T
	TrenchMOS™ standard level FET

120					03aa17
Pder
(%)
80
40
0
	0	50	100	150	200
					Tsp (°C)
P		Ptot
	der	= ---------------------- × 100%
		P	°C )
		tot (25

Fig 1. Normalized total power dissipation as a function of solder point temperature.

120				03aa25
Ider
(%)
80
40
0
0	50	100	150	200
				Tsp (°C)
VGS ³ 10 V

I der	I D
	= ------------------- × 100%
	I D(25	°C )

Fig 2. Normalized continuous drain current as a function of solder point temperature.

102				003aaa234
ID	Limit RDSon = VDS/ID
(A)
10
				tp = 10 µs
				1 ms
1				10 ms
			DC	100 ms
10-1
				1 s
10-2
10-1	1	10	102	103
				VDS (V)

Tsp = 25 °C; IDM is single pulse.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 10773

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 20 January 2003

3 of 12

Philips Semiconductors			PHK4NQ20T
			TrenchMOS™ standard level FET
4. Thermal characteristics
Table 3:	Thermal characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Rth(j-sp)	thermal resistance from junction to solder point	Figure 4	-	-	20	K/W
Rth(j-a)	thermal resistance from junction to ambient	minimum footprint;	-	70	-	K/W
		mounted on printed-circuit board

4.1 Transient thermal impedance

102						003aaa235
Zth(j-sp)
(K/W)	δ = 0.05
10	0.1
	0.05
	0.01
1	0.02
		single pulse			P	tp
10-1						δ = T
					tp	t
						T
10-2
10-4		10-3	10-2	10-1	1	10
						tp (s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

9397 750 10773

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 20 January 2003

4 of 12