Philips PHK4NQ20T User Manual
M3D315
1. Product profile
1.1 Description
1.2 Features
1.3 Applications
PHK4NQ20T
TrenchMOS™ standard level FET
Rev. 01 — 20 January 2003 Product data
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHK4NQ20T in SOT96-1 (SO8).
■ Low on-state resistance
■ Surface mount package.
■ DC-DC primary side switching
■ General purpose switch.
1.4 Quick reference data
■ VDS≤ 200 V ■ ID≤ 4A
■ P
≤ 6.25 W ■ R
tot
DSon
2. Pinning information
Table 1: Pinning - SOT96-1, simplified outline and symbol
Pin Description Simplified outline Symbol
1,2,3 source (s)
4 gate (g)
5,6,7,8 drain (d)
8
1
Top view MBK187
SOT96-1
5
4
≤ 130 mΩ
MBB076
d
g
s
Philips Semiconductors
PHK4NQ20T
TrenchMOS™ standard level FET
3. Limiting values
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 200 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ - 200 V
gate-source voltage (DC) - ±20 V
drain current (DC) Tsp=25°C; VGS=10V;Figure 2 and 3 -4A
= 100 °C; VGS=10V;Figure 2 - 2.58 A
T
sp
peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3 -16A
total power dissipation Tsp=25°C; Figure 1 - 6.25 W
storage temperature −55 +150 °C
junction temperature −55 +150 °C
source (diode forward) current (DC) Tsp=25°C-4A
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs - 16 A
9397 750 10773
Product data Rev. 01 — 20 January 2003 2 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
%
PHK4NQ20T
TrenchMOS™ standard level FET
120
P
der
(%)
80
40
0
0 50 100 150 200
P
tot
P
der
-----------------------
P
tot 25 C°()
100%×=
03aa17
Tsp (°C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
120
I
der
(%)
80
40
0
0 50 100 150 200
03aa25
Tsp (°C)
VGS≥ 10 V
I
I
der
D
-------------------
I
°
D25C
()
100
×=
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
003aaa234
V
(V)
DS
(A)
2
10
I
D
10
1
-1
10
-2
10
-1
10
Limit R
= VDS/I
DSon
D
DC
1 10 10
tp = 10 µs
1 ms
10 ms
100 ms
1 s
2
Tsp=25°C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
10
3
9397 750 10773
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data Rev. 01 — 20 January 2003 3 of 12
Philips Semiconductors
10
-2
10
-1
1
10
10
2
10
-4
10
-3
10
-2
10
-1 1
10
PHK4NQ20T
TrenchMOS™ standard level FET
4. Thermal characteristics
Table 3: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-sp)
R
th(j-a)
thermal resistance from junction to solder point Figure 4 --20K/W
thermal resistance from junction to ambient minimum footprint;
- 70 - K/W
mounted on printed-circuit board
4.1 Transient thermal impedance
003aaa235
Z
th(j-sp)
(K/W)
δ = 0.05
0.1
0.05
0.01
0.02
single pulse
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
t
tp (s)
δ =
p
T
t
P
t
p
T
9397 750 10773
Product data Rev. 01 — 20 January 2003 4 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Loading...