Philips PHB69N03LT, PHD69N03LT, PHP69N03LT Datasheet

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP69N03LT, PHB69N03LT
Logic level FET PHD69N03LT

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

DSS

= 25 V

• Very low on-state resistance

• Fast switching I

D

= 69 A

• Low thermal resistance

• Logic level compatible R

DS(ON)

≤ 12 mΩ (VGS = 10 V)

R

DS(ON)

≤ 14 mΩ (VGS = 5 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-

• High frequency computer motherboard d.c. to d.c. converters

• High current switching
The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB69N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD69N03LT is supplied in the SOT428 (DPAK)surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK) SOT428 (DPAK)

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V

V

DGR

Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V

V

GS

Gate-source voltage (DC) - ± 15 V

V

GSM

Gate-source voltage (pulse Tj ≤ 150˚C - ± 20 V
peak value)

I

D

Drain current (DC) Tmb = 25 ˚C - 69 A

Tmb = 100 ˚C - 48 A

I

DM

Drain current (pulse peak Tmb = 25 ˚C - 240 A
value)

P

tot

Total power dissipation Tmb = 25 ˚C - 125 W

Tj, T

stg

Operating junction and - 55 175 ˚C
storage temperature

d

g

s

123

tab

13

tab

2

123

tab

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

October 1999 1 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP69N03LT, PHB69N03LTT

Logic level FET PHD69N03LT

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction - - 1.2 K/W
to mounting base

R

th j-a

Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W

mounted, minimum footprint

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

R

DS(ON)

Drain-source on-state VGS = 10 V; ID = 25 A - 8.5 12 mΩ
resistance VGS = 5 V; ID = 25 A - 11 14 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 26 mΩ

g

fs

Forward transconductance VDS = 25 V; ID = 25 A 12 40 - S

I

GSS

Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA

I

DSS

Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Q

g(tot)

Total gate charge ID = 69 A; V

DD

= 15 V; VGS = 5 V - 26 - nC

Q

gs

Gate-source charge - 7.6 - nC

Q

gd

Gate-drain (Miller) charge - 11 - nC

t

d on

Turn-on delay time VDD = 15 V; ID = 25 A; - 7 15 ns

t

r

Turn-on rise time VGS = 10 V; RG = 5 Ω -5075ns

t

d off

Turn-off delay time Resistive load - 82 120 ns

t

f

Turn-off fall time - 59 75 ns

L

d

Internal drain inductance Measured tab to centre of die - 3.5 - nH

L

d

Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 1700 - pF

C

oss

Output capacitance - 475 - pF

C

rss

Feedback capacitance - 300 - pF

October 1999 2 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP69N03LT, PHB69N03LTT

Logic level FET PHD69N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

Continuous source current - - 69 A
(body diode)

I

SM

Pulsed source current (body - - 240 A
diode)

V

SD

Diode forward voltage IF = 25 A; VGS = 0 V - 0.9 1.2 V

IF = 69 A; VGS = 0 V - 1.0 -

t

rr

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 83 - ns

Q

rr

Reverse recovery charge VGS = 0 V; VR = 25 V - 0.1 - µC

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb); VGS ≥ 5 V

Fig.3. Safe operating area

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Fig.4. Transient thermal impedance.

Z

th j-mb

= f(t); parameter D = tp/T

Normalised Power Derating, PD (%)

0

10

20

30

40

50

60

70

80

90

100

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

1

10

100

1000

1 10 100

Drain-Source Voltage, VDS (V)

Peak Pulsed Drain Current, IDM (A)

D.C.

100 ms

10 ms

RDS(on) = VDS/ ID

1 ms

tp = 10 us

100 us

Normalised Current Derating, ID (%)

0

10

20

30

40

50

60

70

80

90

100

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

0.01

0.1

1

10

1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

Transient thermal impedance, Zth j-mb (K/W)

single pulse

D = 0.5

0.2

0.1

0.05

0.02

tp

D = tp/T

D

P

T

October 1999 3 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP69N03LT, PHB69N03LTT
Logic level FET PHD69N03LT

Fig.5. Typical output characteristics, Tj = 25 ˚C

.

ID = f(VDS); parameter V

GS

Fig.6. Typical on-state resistance, Tj = 25 ˚C

.

R

DS(ON)

= f(ID); parameter V

GS

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

j

Fig.8. Typical transconductance, Tj = 25 ˚C

.

gfs = f(ID)

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Fig.10. Gate threshold voltage.

V

GS(TO)

= f(Tj); conditions: ID = 1 mA; VDS = V

GS

0

5

10

15

20

25

30

35

40

45

50

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Drain-Source Voltage, VDS (V)

Drain Current, ID (A)

2.2 V

2.4 V

Tj = 25 C

VGS = 10 V

2 V

2.6 V

4.5 V

2.8 V

3 V

5 V

0

5

10

15

20

25

30

35

40

45

50

0 5 10 15 20 25 30 35 40

Drain current, ID (A)

Transconductance, gfs (S)

Tj = 25 C

175 C

VDS > ID X RDS(ON)

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0 5 10 15 20 25 30 35 40 45 50

Drain Current, ID (A)

Drain-Source On Resistance, RDS(on) (Ohms)

VGS =4.5 V

10V

Tj = 25 C

2.8V

3 V

2.6 V

2.2 V 2.4 V

5 V

Normalised On-state Resistance

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

0

5

10

15

20

25

30

35

40

45

50

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Gate-source voltage, VGS (V)

Drain current, ID (A)

VDS > ID X RDS(ON)

Tj = 25 C

175 C

Threshold Voltage, VGS(TO) (V)

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

typical

maximum

minimum

October 1999 4 Rev 1.600