Philips PHD50N03LT, PHP50N03LT Datasheet

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP50N03LT, PHB50N03LT
Logic level FET PHD50N03LT

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 25 V

DSS

• Very low on-state resistance

• Fast switching I

= 48 A

D

• High thermal cycling performance

• Low thermal resistance R

g

≤ 16 mΩ (VGS = 10 V)

DS(ON)

• Logic level compatible

s

R

≤ 21 mΩ (VGS = 5 V)

DS(ON)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-

• High frequency computer motherboard d.c. to d.c. converters

• High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB50N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK) SOT428 (DPAK)

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

tab

123

tab

2

13

tab

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

tot

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

October 1999 1 Rev 1.800

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V
Gate-source voltage (DC) - ± 15 V
Gate-source voltage (pulse Tj ≤ 150˚C - ± 20 V
peak value)
Drain current (DC) Tmb = 25 ˚C - 48 A

Tmb = 100 ˚C - 34 A
Drain current (pulse peak Tmb = 25 ˚C - 180 A
value)
Total power dissipation Tmb = 25 ˚C - 86 W
Operating junction and - 55 175 ˚C

stg

storage temperature

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP50N03LT, PHB50N03LT

Logic level FET PHD50N03LT

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

Thermal resistance junction - - 1.75 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W

mounted, minimum footprint

Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

R

DS(ON)

Drain-source on-state VGS = 10 V; ID = 25 A - 13 16 mΩ
resistance VGS = 10 V; ID = 25 A (SOT428 package) - 15 18 mΩ

VGS = 5 V; ID = 25 A - 18 21 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 39 mΩ

g
I

fs

DSS

Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

I
Q

Q
Q

t
t
t
t

L
L

GSS

g(tot)
gs
gd

d on
r
d off
f

d
d

Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 50 A; V

= 15 V; VGS = 5 V - 17 - nC

DD

Gate-source charge - 7.6 - nC
Gate-drain (Miller) charge - 11 - nC

Turn-on delay time VDD = 15 V; ID = 25 A; - 6.4 12 ns
Turn-on rise time VGS = 10 V; RG = 5 Ω -6275ns
Turn-off delay time Resistive load - 50 75 ns
Turn-off fall time - 30 45 ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF
Output capacitance - 330 - pF
Feedback capacitance - 220 - pF

October 1999 2 Rev 1.800

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP50N03LT, PHB50N03LT

Logic level FET PHD50N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 48 A
(body diode)
Pulsed source current (body - - 180 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 40 A; VGS = 0 V - 1.05 ­Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 100 - ns

Reverse recovery charge VGS = 0 V; VR = 25 V - 0.13 - µC

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

100

10

D.C.

1

1 10 100

Drain-Source Voltage, VDS (V)

tp = 10 us

100 us

1 ms

10 ms
100 ms

Fig.3. Safe operating area

ID & IDM = f(VDS); IDM single pulse; parameter t

Transient thermal impedance, Zth j-mb (K/W)

10

D = 0.5

1

0.2

0.1

0.05

0.1

0.02

single pulse

0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

D = tp/T

tp

T

p

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

October 1999 3 Rev 1.800

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP50N03LT, PHB50N03LT
Logic level FET PHD50N03LT

Drain Current, ID (A)

50
45
40
35
30
25
20
15
10

5
0

VGS = 10 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

5 V

4.5 V

Drain-Source Voltage, VDS (V)

Tj = 25 C

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

Drain-Source On Resistance, RDS(on) (Ohms)

0.1

2.2 V

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01
0

0 5 10 15 20 25 30 35 40 45 50

2.4 V

2.6 V

2.8V
3 V

Drain Current, ID (A)

3.2 V

5 V

GS

Tj = 25 C

VGS =4.5 V

Fig.6. Typical on-state resistance

R

= f(ID); parameter V

DS(ON)

GS

3.2 V

2.6 V

2.4 V

2.2 V

10V

3 V

2.8 V

Transconductance, gfs (S)

30

VDS > ID X RDS(ON)

25

20

15

10

5

0

0 5 10 15 20 25 30 35 40

Tj = 25 C

175 C

Drain current, ID (A)

Fig.8. Typical transconductance

gfs = f(ID)

Normalised On-state Resistance

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1
1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Drain current, ID (A)

40

VDS > ID X RDS(ON)

35

30

25

20

15

10

5

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

175 C

Gate-source voltage, VGS (V)

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS)

Threshold Voltage, VGS(TO) (V)

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

GS

October 1999 4 Rev 1.800