Philips phd3n20l DATASHEETS

Philips Semiconductors Product specification

PowerMOS transistor PHD3N20L
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope suitable for surface V
mounting featuring high avalanche I
energy capability, stable blocking P
voltage, fast switching and high R
thermalcyclingperformancewithlow

DS

D

tot

DS(ON)

thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.

PINNING - SOT428 PIN CONFIGURATION SYMBOL

Drain-source voltage 200 V
Drain current (DC) 3.5 A
Total power dissipation 50 W
Drain-source on-state resistance 1.5 Ω

PIN DESCRIPTION

tab

d

1 gate
2 drain

g

3 source

tab drain

2

1

3

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

I

D

I

DM

P

D

∆PD/∆TmbLinear derating factor Tmb > 25 ˚C - 0.33 W/K
V

GS

V

GSM

E

AS

I

AS

Tj, T

Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 3.5 A

Tmb = 100 ˚C; VGS = 10 V - 2.5 A
Pulsed drain current Tmb = 25 ˚C - 14 A
Total dissipation Tmb = 25 ˚C - 50 W

Gate-source voltage - ± 15 V
Non-repetitive gate-source tp ≤ 50 µs-± 20 V
voltage
Single pulse avalanche VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; - 25 mJ
energy VGS = 5 V
Peak avalanche current VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; - 3.5 A

VGS = 5 V
Operating junction and - 55 175 ˚C

stg

storage temperature range

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

September 1997 1 Rev 1.000

Thermal resistance junction to - 3 K/W
mounting base
Thermal resistance junction to pcb mounted, minimum 50 - K/W
ambient footprint

Philips Semiconductors Product specification

PowerMOS transistor PHD3N20L
Logic level FET

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

∆V

(BR)DSS

∆T

j

R

DS(ON)

V

GS(TO)

g

fs

I

DSS

I

GSS

Q

g(tot)

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 200 - - V
voltage

/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.25 - V/K

voltage temperature coefficient
Drain-source on resistance VGS = 5 V; ID = 2 A - 0.77 1.5 Ω
Gate threshold voltage VDS = VGS; ID = 0.25 mA 1.0 1.5 2.0 V
Forward transconductance VDS = 50 V; ID = 2 A 0.8 3.0 - S
Drain-source leakage current VDS = 200 V; VGS = 0 V - 0.1 25 µA

VDS = 160 V; VGS = 0 V; Tj = 150 ˚C - 1 250 µA

Gate-source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 3.3 A; V

Gate-source charge - 1 3 nC

= 160 V; VGS = 5 V - 7.5 9 nC

DD

Gate-drain (Miller) charge - 4 6 nC
Turn-on delay time VDD = 100 V; ID = 3.3 A; - 8 - ns

Turn-on rise time RG = 24 Ω; RD = 30 Ω -33-ns
Turn-off delay time - 40 - ns
Turn-off fall time - 36 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal source inductance Measured from source lead solder - 7.5 - nH

point to source bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 270 - pF
Output capacitance - 48 - pF
Feedback capacitance - 17 - pF

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current Tmb = 25˚C - - 3.5 A
(body diode)
Pulsed source current (body Tmb = 25˚C - - 14 A
diode)
Diode forward voltage IS = 3.3 A; VGS = 0 V - - 1.5 V

Reverse recovery time IS = 3.3 A; VGS = 0 V; - 90 - ns

dI/dt = 100 A/µs

Reverse recovery charge - 0.5 - µC

September 1997 2 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor PHD3N20L
Logic level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Zth j-mb, Transient Thermal Impedance (K/W)

10

0.5

1

0.2

0.1

0.05

0.1

0.01

0.02

0

1us

10us 1ms

tp, pulse widtht (s)

t

P

p

D

T

0.1s

D =

t

p

T

t

1s10ms100us

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

ID, Drain current (Amps)

8
7

Tj = 25 C

6
5
4
3
2
1
0

0 5 10 15 20 25 30

VDS, Drain-Source voltage (Volts)

5 V

10 V

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

PHP2N20L

3.5 V

3 V

VGS = 2.5 V

.

GS

10s

4 V

ID, Drain current (Amps)

100

10

RDS(ON) = VDS/ID

1

0.1
1 10 100 1000

VDS, Drain-source voltage (Volts)

DC

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

PHP2N20E

tp = 10 us

100 us

1 ms
10 ms

100 ms

RDS(on), Drain-Source on resistance (Ohms)

4

3

2

1

0

012345678

2.5 V

Tj = 25 C

ID, Drain current (Amps)

3 V 3.5 V 4 V

Fig.6. Typical on-state resistance

R

p

= f(ID); parameter V

DS(ON)

PHP2N20L

5 V

VGS = 10 V

.

GS

September 1997 3 Rev 1.000