Philips PHD24N03LT Datasheet

Philips Semiconductors Preliminary specification

TrenchMOS transistor PHD24N03LT
Logic level FET

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 30 V

DSS

• Very low on-state resistance

• Fast switching I

= 24 A

D

• Stable off-state characteristics

• High thermal cycling performance R

g

≤ 56 mΩ (VGS = 5 V)

DS(ON)

• Low thermal resistance

s

R

≤ 50 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION PINNING SOT428 (DPAK)

N-channel enhancement mode, PIN DESCRIPTION
logic level, field-effect power
transistor in a plastic envelope 1 gate
using ’trench’ technology. The
device has very low on-state 2 drain

1

resistance. It is intended for use in
dc to dc converters and general 3 source
purpose switching applications.

tab drain
ThePHD24N03LTissuppliedinthe
SOT428 (DPAK) surface mounting
package.

tab

2

1

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

3

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
Gate-source voltage - ± 13 V
Continuous drain current Tmb = 25 ˚C - 24 A

Tmb = 100 ˚C - 20 A

I

DM

P

D

Tj, T

Pulsed drain current Tmb = 25 ˚C - 96 A
Total power dissipation Tmb = 25 ˚C - 60 W
Operating junction and - 55 175 ˚C

stg

storage temperature

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

1 it is not possible to make connection to pin 2 of the SOT428 package.

Thermal resistance junction - 2.5 K/W
to mounting base
Thermal resistance junction pcb mounted, minimum footprint 50 - K/W
to ambient

December 1999 1 Rev 1.100

Philips Semiconductors Preliminary specification

TrenchMOS transistor PHD24N03LT

Logic level FET

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 12 A - 50 56 mΩ
resistance VGS = 5 V; ID = 12 A - 45 50 mΩ

Tj = 175˚C - - 104 mΩ
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 24 A; V

= 15 V; VGS = 5 V - 7 - nC

DD

Gate-source charge - 2.3 - nC
Gate-drain (Miller) charge - 5 - nC

Turn-on delay time VDD = 15 V; RD = 0.6 Ω; - 12 - ns
Turn-on rise time VGS = 5 V; RG = 10 Ω -50-ns
Turn-off delay time Resistive load - 30 - ns
Turn-off fall time - 36 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 460 - pF
Output capacitance - 144 - pF
Feedback capacitance - 78 - pF

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

Continuous source current - - 24 A
(body diode)

I

SM

Pulsed source current (body - - 96 A
diode)

V

SD

t

rr

Q

rr

Diode forward voltage IF = 24 A; VGS = 0 V - 1.05 1.5 V
Reverse recovery time IF = 12 A; -dIF/dt = 100 A/µs; - 50 - ns

Reverse recovery charge VGS = 0 V; VR = 30 V - 100 - nC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

December 1999 2 Rev 1.100

Drain-source non-repetitive ID = 12 A; VDD ≤ 15 V; VGS = 5 V; - 15 mJ
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy

Philips Semiconductors Preliminary specification

TrenchMOS transistor PHD24N03LT
Logic level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

p

t

T

PHP24N03T

p

t

D =

T

t

Transient thermal impedance, Zth j-mb (K/W)

10

D =

0.5

1

0.2

0.1

0.05

0.1

0.02
0

0.01
1us 10us 100us 1ms 10ms 0.1s 1s 10s

pulse width, tp (s)

P

D

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

ID, Drain current (Amps)

20

5 V

15 V

15

10

5

0

0 5 10 15 20 25 30

VDS, Drain-Source voltage (Volts)

PHP24N03LT

3.5 V

3 V

VGS = 2.5 V

Tj = 25 C

Fig.5. Typical output characteristics, Tj = 25 ˚C.

ID = f(VDS); parameter V

GS

ID, Drain current (Amps)

100

RDS(ON) = VDS/ID

10

DC

Tmb = 25 C

1

1 10 100

VDS, Drain-source voltage (Volts)

PHP24N03T

10 us

100 us

1 ms

10 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

RDS(on), Drain-Source on resistance (Ohms)

0.12

0.1

0.08

0.06

0.04

0.02

VGS = 2.5 V

Tj = 25 C

0

0 5 10 15 20

ID, Drain current (Amps)

Fig.6. Typical on-state resistance, Tj = 25 ˚C.

R

p

= f(ID); parameter V

DS(ON)

PHP24N03LT

3 V

3.5 V

5 V

15 V

GS

December 1999 3 Rev 1.100