Philips PHB23NQ10T, PHD23NQ10T, PHP23NQ10T Datasheet

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP23NQ10T, PHB23NQ10T
PHD23NQ10T

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology

• Low on-state resistance V

d

= 100 V

DSS

• Fast switching

• Low thermal resistance I

g

s

R

DS(ON)

= 23 A

D

≤ 70 mΩ

GENERAL DESCRIPTION

N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-

• d.c. to d.c. converters

• switched mode power supplies

• T.V. and computer monitor power supplies
The PHP23NQ10T is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB23NQ10T is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD23NQ10T is supplied in the SOT428 (DPAK) surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK) SOT428 (DPAK)

PIN DESCRIPTION

1 gate

tab

tab

tab

2 drain
3 source

1

2

123

13

123

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

Drain-source voltage Tj = 25 ˚C to 175˚C - 100 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 V
Gate-source voltage - ± 20 V
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 23 A

Tmb = 100 ˚C; VGS = 10 V - 16 A
Pulsed drain current Tmb = 25 ˚C - 92 A
Total power dissipation Tmb = 25 ˚C - 100 W
Operating junction and - 55 175 ˚C

stg

storage temperature

August 1999 1 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP23NQ10T, PHB23NQ10T

PHD23NQ10T

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 14 A; - 93 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer

to fig:15
Peak non-repetitive - 23 A
avalanche current

Thermal resistance junction - - 1.5 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W

footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2 3 4 V

Tj = 175˚C 1 - - V

Tj = -55˚C - - 6 V
Drain-source on-state VGS = 10 V; ID = 13 A - 49 70 mΩ
resistance Tj = 175˚C - 132 189 mΩ
Gate source leakage current VGS = ± 20 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 100 V; VGS = 0 V - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 23 A; V

= 80 V; VGS = 10 V - 22 - nC

DD

Gate-source charge - 5 - nC
Gate-drain (Miller) charge - 10 - nC

Turn-on delay time VDD = 50 V; RD = 2.2 Ω;-8-ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω -39-ns
Turn-off delay time Resistive load - 26 - ns
Turn-off fall time - 24 - ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 890 1187 pF
Output capacitance - 139 167 pF
Feedback capacitance - 83 109 pF

August 1999 2 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP23NQ10T, PHB23NQ10T

PHD23NQ10T

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 23 A
(body diode)
Pulsed source current (body - - 92 A
diode)
Diode forward voltage IF = 11 A; VGS = 0 V - 0.9 1.2 V

Reverse recovery time IF = 11 A; -dIF/dt = 100 A/µs; - 64 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 120 - nC

August 1999 3 Rev 1.100

Philips Semiconductors Product specification

Drain-S

RDS(on) (Ohms)

N-channel TrenchMOS transistor PHP23NQ10T, PHB23NQ10T
PHD23NQ10T

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Transient thermal impedance, Zth j-mb (K/W)

10

D = 0.5

1

0.2

0.1

0.05

0.1

0.02

single pulse

0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

tp

D = tp/T

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

55
50
45
40
35
30
25
20
15
10

5
0

012345678910

9 V

Drain-Source Voltage, VDS (V)

8 V

7 V

6 V

5 V

4V

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

100

10

1

0.1
1 10 100 1000

= f(Tmb); conditions: VGS ≥ 10 V

D 25 ˚C

tp = 10 us

100 us

D.C.

Drain-Source Voltage, VDS (V)

1 ms
10 ms

100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

Fig.6. Typical on-state resistance, Tj = 25 ˚C

ource On Resistance,

4V

5.5V

5 V

0 1020304050

6V

6.5V

Drain Current, ID (A)

7 V

VGS =9 V

8V

.

R

= f(ID)

DS(ON)

.

August 1999 4 Rev 1.100