Philips PHC20512 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

PHC20512

Complementary enhancement
mode
MOS transistors

Product specification
Supersedes data of 1997 Jun 19
File under Discrete Semiconductors, SC13b

1997 Oct 22

Philips Semiconductors Product specification

Complementary enhancement mode
MOS transistors

FEATURES

• High-speed switching

• No secondary breakdown

• Very low on-state resistance.

APPLICATIONS

• Motor and actuator driver

• Power management

• Synchronized rectification.

DESCRIPTION

One N-channel and one P-channel enhancement mode
MOS transistor in an 8-pin plastic SOT96-1 (SO8)
package.

CAUTION

The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.

PINNING - SOT96-1 (SO8)

PIN SYMBOL DESCRIPTION

1s
2g
3s
4g
5d
6d
7d
8d

handbook, halfpage

58

1

4

MAM118

1
1
2
2
2
2
1
1

source 1
gate 1
source 2
gate 2
drain 2
drain 2
drain 1
drain 1

d

d

1

1

g

s

1

Fig.1 Simplified outline and symbol.

PHC20512

d

d

2

2

g

s

1

2

2

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per channel

V

DS

drain-source voltage (DC)

N-channel − 30 V
P-channel −−30 V

V

V
V

I

D

SD

GS
GSth

source-drain diode forward voltage

N-channel I
P-channel I

= 1.25 A − 1V

S

= −1.25 A −−1.3 V

S

gate-source voltage (DC) −±20 V
gate-source threshold voltage

N-channel V
P-channel V

DS=VGS;ID
DS=VGS

= 1 mA 1 2.8 V

; ID= −1mA −1 −2.8 V

drain current (DC) Ts=80°C

N-channel − 6.4 A
P-channel −−4A

R

DSon

P

tot

drain-source on-state resistance

N-channel V
P-channel V

=10V; ID= 3.2 A − 0.05 Ω

GS

= −10 V ID= −2A − 0.12 Ω

GS

total power dissipation Ts=80°C − 3.5 W

1997 Oct 22 2

Philips Semiconductors Product specification

Complementary enhancement mode

PHC20512

MOS transistors

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per channel

V

DS

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage (DC)

N-channel − 30 V

P-channel −−30 V
gate-source voltage (DC) −±20 V
drain current (DC) Ts=80°C; note 1

N-channel − 6.4 A

P-channel −−4A
peak drain current note 2

N-channel − 25 A

P-channel −−16 A
total power dissipation Ts=80°C; note 3 − 3.5 W

T

=25°C; note 4 − 2.6 W

amb

T

=25°C; note 5 − 1.1 W

amb

T

=25°C; note 6 − 1.5 W

amb

storage temperature −65 +150 °C
operating junction temperature −65 +150 °C

source current (DC) Ts=80°C

N-channel − 3.5 A

P-channel −−2.6 A
peak pulsed source current note 2

N-channel − 14 A

P-channel −−10 A

Notes

is the temperature at the soldering point of the drain lead.

1. T

s

2. Pulse width and duty cycle limited by maximum junction temperature.

3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.

4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R

th a-tp

(ambient to tie-point) of 27.5 K/W.

5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R

th a-tp

(ambient to tie-point) of 90 K/W.

6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an R

(ambient to tie-point) of 90 K/W.

th a-tp

1997 Oct 22 3

Philips Semiconductors Product specification

Complementary enhancement mode
MOS transistors

handbook, halfpage

8

P

tot

(W)

6

4

2

0

0 50 100 150

MGG340

Ts (°C)

2

10

handbook, halfpage

I

D

(A)

10

P

1

−1

10

−1

10

PHC20512

MGG341

tp =

(1)

t

p

δ =

T

t

p

T

t

11010

10 µs
100 µs

1 ms
10 ms

100 ms
DC

V

DS

(V)

2

2

−10

handbook, halfpage

I

D

(A)

−10

−1

−1

−10

−1

−10

Fig.2 Power derating curve.

(1)

t

P

t

p

p

δ =

T

t

T

−1 −10 −10
VDS (V)

MBH587

tp =

10 µs
100 µs

1 ms
10 ms

100 ms
DC

δ =0.01; Ts=80°C.
(1) R

DSon

limitation.

Fig.3 SOAR; N-channel.

2

δ = 0.01; Ts=80°C.
(1) R

DSon

limitation.

Fig.4 SOAR; P-channel.

1997 Oct 22 4

Philips Semiconductors Product specification

Complementary enhancement mode

PHC20512

MOS transistors

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-s

CHARACTERISTICS

=25°C unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per channel

V

(BR)DSS

V

GSth

I

DSS

I

GSS

R

DSon

C

iss

C

oss

C

rss

Q

G

Q

GS

thermal resistance from junction to soldering point 20 K/W

drain-source breakdown voltage

N-channel V
P-channel V

= 0; ID=10µA30−−V

GS

= 0; ID= −10 µA −30 −−V

GS

gate-source threshold voltage

N-channel V
P-channel V

GS=VDS
GS=VDS

; ID= 1 mA 1 − 2.8 V
; ID= −1mA −1 −−2.8 V

drain-source leakage current

N-channel V
P-channel V

= 0; VDS=24V −−100 nA

GS

= 0; VDS= −24 V −−−100 nA

GS

gate leakage current VGS= ±20 V; VDS=0

N-channel −−±100 nA
P-channel −−±100 nA

drain-source on-state resistance

N-channel V

P-channel V

= 4.5 V; ID= 1.6 A −−0.1 Ω

GS

V

= 10 V; ID= 3.2 A −−0.05 Ω

GS

= −4.5 V; ID= −1A −−0.25 Ω

GS

V

= −10 V; ID= −2A −−0.12 Ω

GS

input capacitance

N-channel V
P-channel V

= 0; VDS=24V; f=1MHz − 450 − pF

GS

= 0; VDS= −24 V; f = 1 MHz − 450 − pF

GS

output capacitance

N-channel V
P-channel V

= 0; VDS=24V; f=1MHz − 200 − pF

GS

= 0; VDS= −24 V; f = 1 MHz − 200 − pF

GS

reverse transfer capacitance

N-channel V
P-channel V

= 0; VDS=24V; f=1MHz − 100 − pF

GS

= 0; VDS= −24 V; f = 1 MHz − 100 − pF

GS

total gate charge

N-channel V
P-channel V

= 10 V; VDD= 15 V; ID= 3.2 A − 15 − nC

GS

= −10 V; VDD= −15 V; ID= −2A − 13 − nC

GS

gate-source charge

N-channel V
P-channel V

= 10 V; VDD= 15 V; ID= 3.2 A − 1 − nC

GS

= −10 V; VDD= −15 V; ID= −2A − 1 − nC

GS

1997 Oct 22 5

Philips Semiconductors Product specification

Complementary enhancement mode

PHC20512

MOS transistors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Q

GD

t

d(on)

t

d(off)

t

f

t

r

t

on

t

off

Source-drain diode

V

SD

t

rr

gate-drain charge

N-channel V
P-channel V

turn-on delay time

N-channel V

P-channel V

turn-off delay time

N-channel V

P-channel V

fall time

N-channel V

P-channel V

rise time

N-channel V

P-channel V

turn-on switching time

N-channel V

P-channel V

turn-off switching time

N-channel V

P-channel V

source-drain diode forward
voltage

N-channel V
P-channel V

reverse recovery time

N-channel I
P-channel I

= 10 V; VDD= 15 V; ID= 3.2 A − 5 − nC

GS

= −10 V; VDD= −15 V; ID= −2A − 4 − nC

GS

= 0to10V; VDD=15V; ID=1A;

GS

R

=6Ω

gen

=0to−10 V; VDD= −15 V;

GS

ID= −1 A; R

=10to0V; VDD=15V;

GS

ID= 1 A; R

= −10 to 0 V; VDD= −15 V;

GS

ID= −1 A; R

= 0to10V; VDD=15V; ID=1A;

GS

R

=6Ω

gen

= −10 to 0 V; VDD= −15 V;

GS

ID= −1 A; R

=10to0V; VDD=15V; ID=1A;

GS

R

=6Ω

gen

=0to−10 V; VDD= −15 V;

GS

ID= −1 A; R

= 0to10V; VDD=15V; ID=1A;

GS

R

=6Ω

gen

=0to−10 V; VDD= −15 V;

GS

ID= −1 A; R

=10to0V; VDD=15V;

GS

ID= 1 A; R

= −10 to 0 V; VDD= −15 V;

GS

ID= −1 A; R

= 0; IS= 1.25 A −−1V

GD

= 0; IS= −1.25 A −−−1.3 V

GD

= 1.25 A; di/dt = −100 A/µs − 45 − ns

S

= −1.25 A; di/dt = 100 A/µs − 75 − ns

S

gen

gen

gen

gen

gen

gen

gen

gen

=6Ω

=6Ω

=6Ω

=6Ω

=6Ω

=6Ω

=6Ω

=6Ω

− 7 − ns

− 6 − ns

− 20 − ns

− 29 − ns

− 8 − ns

− 16 − ns

− 12 − ns

− 4 − ns

− 15 − ns

− 10 − ns

− 32 − ns

− 45 − ns

1997 Oct 22 6