Philips PHP71NQ03LT, PHB71NQ03LT, PHD71NQ03LT User Guide

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

Rev. 01 — 25 June 2002

Product data

1.Product profile

1.1Description

N-channel enhancement mode field-effect transistor in a plastic package using

TrenchMOS™ technology.

Product availability:

PHP71NQ03LT in SOT78 (TO-220AB)

PHB71NQ03LT in SOT404 (D2-PAK)

PHD71NQ03LT in SOT428 (D-PAK).

1.2

Features

■ Logic level compatible

■ Low gate charge

1.3

Applications

■ DC to DC converters

■ Switched mode power supplies

1.4

Quick reference data

■ VDS = 30 V

■ ID = 75 A

■ Ptot = 120 W

■ RDSon ≤ 10 mΩ

2.

Pinning information

Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol

Pin

Description

Simplified outline

Symbol

1

gate (g)

mb

mb

mb

d

2

drain (d)

[1]

3

source (s)

mb

mounting base,

g

connected to drain (d)

2

MBB076 s

1

2

3 MBK116

1

3

MBK106

Top view

MBK091

1

2

3

SOT78 (TO-220)

SOT404 (D2-PAK)

SOT428 (D-PAK)

[1]It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.

Philips Semiconductors	PHP/PHB/PHD71NQ03LT
	TrenchMOS™ logic level FET

3. Limiting values

Table 2: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol	Parameter	Conditions		Min	Max	Unit
VDS	drain-source voltage (DC)	25 °C ≤ Tj ≤ 175 °C		-	30	V
VDGR	drain-gate voltage (DC)	25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ		-	30	V
VGS	gate-source voltage (DC)			-	±20	V
VGSM	peak gate-source voltage	tp ≤ 50 μs; pulsed; duty cycle = 25 %		-	±25	V
ID	drain current (DC)	Tmb = 25 °C; VGS = 10 V; Figure 2 and 3		-	75	A
		Tmb = 100 °C; VGS = 10 V; Figure 2		-	57.7	A
IDM	peak drain current	Tmb = 25	°C; pulsed; tp ≤ 10 μs; Figure 3	-	240	A
Ptot	total power dissipation	Tmb = 25	°C; Figure 1	-	120	W
Tstg	storage temperature			−55	+175	°C
Tj	junction temperature			−55	+175	°C
Source-drain diode
IS	source (diode forward) current (DC)	Tmb = 25	°C	-	75	A
ISM	peak source (diode forward) current	Tmb = 25	°C; pulsed; tp ≤ 10 μs	-	57.7	A

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data

Rev. 01 — 25 June 2002

2 of 14

Philips Semiconductors	PHP/PHB/PHD71NQ03LT
	TrenchMOS™ logic level FET

120						03aa16
Pder
(%)
	80
	40
	0
		0	50	100	150	200
					Tmb (°C)
P		=	Ptot	× 100%
	der		----------------------
			P
			tot (25°C )

Fig 1. Normalized total power dissipation as a function of mounting base temperature.

120					03ai74
Ider
(%)
80
40
0
	0	50	100	150	200
					Tmb (°C)
I der		I D
	= ------------------- × 100%
		I D(25°C )

Fig 2. Normalized continuous drain current as a function of mounting base temperature.

103		03ai76
ID
(A)	Limit RDSon = VDS / ID	tp = 10 μs
102		100 μs
	DC	1 ms
10
		10 ms
1		102
1	10
		VDS (V)

Tmb = 25 °C; IDM is single pulse; VGS = 10V.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data

Rev. 01 — 25 June 2002

3 of 14

Philips Semiconductors		PHP/PHB/PHD71NQ03LT
			TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:	Thermal characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Rth(j-mb)	thermal resistance from junction to mounting base	Figure 4	-	-	1.25	K/W
Rth(j-a)	thermal resistance from junction to ambient
	SOT78	vertical in still air	-	60	-	K/W
	SOT428	SOT428 minimum footprint;	-	75	-	K/W
		mounted on a PCB
	SOT404 and SOT428	SOT404 minimum footprint;	-	50	-	K/W
		mounted on a PCB

4.1 Transient thermal impedance

10				03ai75
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1			P	tp
0.05				δ = T
0.02
	single pulse		tp	t
				T
10-2
10-5	10-4	10-3	10-2	10-1
				tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data

Rev. 01 — 25 June 2002

4 of 14

Philips Semiconductors	PHP/PHB/PHD71NQ03LT
	TrenchMOS™ logic level FET

5. Characteristics

Table 4: Characteristics

Tj = 25 °C unless otherwise specified

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Static characteristics
V(BR)DSS	drain-source breakdown voltage	ID = 250 μA; VGS = 0 V
		Tj = 25 °C	30	-	-	V
		Tj = −55 °C	27	-	-	V
VGS(th)	gate-source threshold voltage	ID = 1 mA; VDS = VGS; Figure 9
		Tj = 25 °C	1	1.9	2.5	V
		Tj = 175 °C	0.6	-	-	V
		Tj = −55 °C	-	-	2.9	V
IDSS	drain-source leakage current	VDS = 30 V; VGS = 0 V
		Tj = 25 °C	-	0.05	1	μA
		Tj = 175 °C	-	-	500	μA
IGSS	gate-source leakage current	VGS = ±20 V; VDS = 0 V	-	10	100	nA
RDSon	drain-source on-state resistance	VGS = 5 V; ID = 25 A; Figure 7 and 8
		Tj = 25 °C	-	12	15.2	mΩ
		Tj = 175 °C	-	21.6	27.4	mΩ
		VGS = 10 V; ID = 25 A; Figure 7	-	8	10	mΩ
Dynamic characteristics
Qg(tot)	total gate charge	ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13	-	13.2	-	nC
Qgs	gate-source charge		-	5.3	-	nC
Qgd	gate-drain (Miller) charge		-	4.6	-	nC
Ciss	input capacitance	VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11	-	1220	-	pF
Coss	output capacitance		-	330	-	pF
Crss	reverse transfer capacitance		-	140	-	pF
td(on)	turn-on delay time	VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 Ω	-	15	-	ns
tr	rise time		-	150	-	ns
td(off)	turn-off delay time		-	13.5	-	ns
tf	fall time		-	18	-	ns
Source-drain diode
VSD	source-drain (diode forward) voltage	IS = 25 A; VGS = 0 V; Figure 12	-	0.9	1.2	V
trr	reverse recovery time	IS = 10 A; dIS/dt = −100 A/μs; VGS = 0 V	-	29	-	ns
Qr	recovered charge		-	20	-	nC

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data

Rev. 01 — 25 June 2002

5 of 14