Philips PHB65N06T Datasheet

Philips Semiconductors Product specification
TrenchMOS transistor PHB65N06T Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT standard level field-effect power transistor in a plastic envelope V suitable for surface mounting. Using I ’trench technology the device P featuresverylow on-state resistance T and has integral zener diodes giving R
DS
D
tot j
DS(ON)
ESD protection up to 2kV. It is resistance VGS = 10 V intended for use in DC-DC converters and general purpose switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
mb
d
1 gate 2 drain 3 source
mb drain
2
13
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V V ±V I
D
I
D
I
DM
P T
DS DGR
tot
stg
GS
, T
j
Drain-source voltage - - 55 V Drain-gate voltage RGS = 20 k -55V Gate-source voltage - - 20 V Drain current (DC) Tmb = 25 ˚C - 63 A Drain current (DC) Tmb = 100 ˚C - 44 A Drain current (pulse peak value) Tmb = 25 ˚C - 240 A Total power dissipation Tmb = 25 ˚C - 150 W Storage & operating temperature - - 55 175 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model - 2 kV voltage, all pins (100 pF, 1.5 k)
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
R
th j-a
November 1997 1 Rev 1.100
Thermal resistance junction to - - 1.0 K/W mounting base Thermal resistance junction to Minimum footprint, FR4 50 - K/W ambient board
Philips Semiconductors Product specification
TrenchMOS transistor PHB65N06T
Standard level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V R
DS(ON)
(BR)GSS
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V voltage Tj = -55˚C 50 - - V Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - V
Tj = -55˚C - - 4.4 V
Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - - 20 µA Gate-source breakdown IG = ±1 mA; 16 - - V voltage Drain-source on-state VGS = 10 V; ID = 25 A - 15 18 m resistance Tj = 175˚C - - 38 m
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g Q
Q Q
C C C
t t t t
L
fs
g(tot) gs gd
iss oss rss
d on r d off f
d
Forward transconductance VDS = 25 V; ID = 25 A 6 30 - S Total gate charge ID = 50 A; V
= 44 V; VGS = 10 V - 37 - nC
DD
Gate-source charge - 10 - nC Gate-drain (Miller) charge - 14 - nC
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1500 2000 pF Output capacitance - 370 470 pF Feedback capacitance - 170 250 pF
Turn-on delay time VDD = 30 V; ID = 25 A; - 15 22 ns Turn-on rise time VGS = 10 V; RG = 10 - 3060ns Turn-off delay time Resistive load - 35 50 ns Turn-off fall time - 25 38 ns
Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die
L
s
Internal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
t
rr
Q
SD
rr
Continuous reverse drain - - 63 A current Pulsed reverse drain current - - 240 A Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 50 A; VGS = 0 V - 1.0 - V
Reverse recovery time IF = 50 A; -dIF/dt = 100 A/µs; - 48 - ns Reverse recovery charge VGS = -10 V; VR = 30 V - 0.1 - µC
November 1997 2 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor PHB65N06T
Standard level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
Drain-source non-repetitive ID = 50 A; VDD 25 V; - - 125 mJ unclamped inductive turn-off VGS = 10 V; RGS = 50 ; Tmb = 25 ˚C energy
November 1997 3 Rev 1.100
Loading...
+ 5 hidden pages