Philips PHB55N03LTA, PHD55N03LTA Datasheet
1. Description
2. Features
PHP55N03LTA;PHB55N03LTA;
PHD55N03LTA
N-channel enhancement mode field-effect transistor
Rev. 02 — 2 August 2001 Product data
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHP55N03LTA in a SOT78 (TO-220AB)
PHB55N03LTA in a SOT404 (D
PHD55N03LTA in a SOT428 (D-PAK).
■ Low on-state resistance
■ Fast switching.
2
-PAK)
3. Applications
■ Computer motherboard high frequency DC to DC converters.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
2 drain (d)
3 source (s)
mb mounting base,
connected to drain (d)
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
[1]
MBK106
12mb3
SOT78 (TO-220AB) SOT404 (D2-PAK) SOT428 (D-PAK)
mb
2
13
MBK116
mb
2
13
Top view
MBK091
MBB076
d
g
s
1. TrenchMOS is a trademark of Royal Phillips Electronics.
Philips Semiconductors
PHP55N03LTA series
N-channel enhancement mode field-effect transistor
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
V
I
D
P
T
R
DS
tot
j
DSon
drain-source voltage (DC) Tj=25to175°C - 25 V
drain current (DC) Tmb=25°C; VGS=5V - 55 A
total power dissipation Tmb=25°C - 85 W
junction temperature - 175 °C
drain-source on-state resistance VGS= 10 V; ID= 25 A; Tj=25°C 1114mΩ
=5V; ID= 25 A; Tj=25°C 1518mΩ
V
GS
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
Avalanche ruggedness
E
AS
I
AS
drain-source voltage (DC) Tj=25to175°C - 25 V
drain-gate voltage (DC) Tj=25to175°C; RGS=20kΩ -25V
gate-source voltage (DC) - ±15 V
gate-source voltage tp≤ 50 µs pulsed;
duty cycle 25%; T
≤ 150 °C
j
- ±20 V
drain current (DC) Tmb=25°C; VGS=5V;Figure 2 and 3 -55A
= 100 °C; VGS=5V;Figure 2 -38A
T
mb
peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; Figure 3 - 220 A
total power dissipation Tmb=25°C; Figure 1 -85W
storage temperature −55 +175 °C
operating junction temperature −55 +175 °C
source (diode forward) current (DC) Tmb=25°C - 55 A
peak source (diode forward) current Tmb=25°C; pulsed; tp≤ 10 µs - 220 A
non-repetitive avalanche energy unclamped inductive load; ID=55A;
= 0.1 ms; VDD=15V; RGS=50Ω;
t
p
= 5V; starting Tj=25°C
V
GS
non-repetitive avalanche current unclamped inductive load; VDD=15V;
=50Ω; VGS= 5 V; starting Tj=25°C
R
GS
-60mJ
- 55 A
9397 750 08642
Product data Rev. 02 — 2 August 2001 2 of 14
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Philips Semiconductors
PHP55N03LTA series
N-channel enhancement mode field-effect transistor
150
03aa16
200
Tmb (oC)
120
P
der
(%)
80
40
0
0
P
----------------------
der
P
tot 25 C°()
P
tot
50 100
100%×= I
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
3
10
120
I
der
(%)
80
40
0
0 50 100 150 200
I
D
der
------------------ -
I
D25C°()
100%×=
03aa24
T
(oC)
mb
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ae64
I
D
(A)
2
10
10
1
P
t
p
1 10 10
R
= V
/ I
DS
D
D.C.
tp = 10 µs
100 µs
1 ms
10 ms
100 ms
2
VDS (V)
DSon
t
p
δ =
T
t
T
Tmb=25°C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 08642
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data Rev. 02 — 2 August 2001 3 of 14
Philips Semiconductors
PHP55N03LTA series
N-channel enhancement mode field-effect transistor
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Value Unit
R
th(j-mb)
R
th(j-a)
thermal resistance from junction to mounting
base
thermal resistance from junction to ambient vertical in still air; SOT78 package 60 K/W
7.1 Transient thermal impedance
Figure 4 1.75 K/W
mounted on a printed circuit board; minimum
50 K/W
footprint; SOT404 and SOT428 packages
10
Z
th(j-mb)
(K/W)
1
10
10
δ = 0.5
0.2
0.1
-1
0.05
0.02
single pulse
-2
10
-5
10
-4
10
-3
10
-2
10
P
t
p
-1
03ae63
t
p
δ =
T
t
T
1
(s)
t
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 08642
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data Rev. 02 — 2 August 2001 4 of 14
Philips Semiconductors
PHP55N03LTA series
N-channel enhancement mode field-effect transistor
8. Characteristics
Table 5: Characteristics
Tj=25°C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
V
GS(th)
I
DSS
I
GSS
R
DSon
Dynamic characteristics
g
fs
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Source-drain diode
V
SD
drain-source breakdown voltage ID= 0.25 mA; VGS=0V
=25°C 25--V
T
j
= −55 °C 22--V
T
j
gate-source threshold voltage ID= 1 mA; VDS=VGS; Figure 9
=25°C 1 1.5 2 V
T
j
= 175 °C 0.5 - - V
T
j
= −55 °C - - 2.3 V
T
j
drain-source leakage current VDS=25V; VGS=0V
=25°C - 0.05 10 µA
T
j
= 175 °C - - 500 µA
T
j
gate-source leakage current VGS= ±5 V; VDS= 0 V - 10 100 nA
drain-source on-state resistance VGS=5V; ID=25A;Figure 7 and 8
=25°C - 15 18 mΩ
T
j
= 175 °C - 25.5 30.6 mΩ
T
j
= 10 V; ID=25A
V
GS
=25°C - 11 14 mΩ
T
j
forward transconductance VDS=25V; ID=25A - 32 - S
total gate charge ID= 55 A; VDD=15V; VGS=5V;
gate-source charge - 8 - nC
Figure 13
-20-nC
gate-drain (Miller) charge - 7 - nC
input capacitance VGS=0V; VDS= 25 V; f = 1 MHz;
output capacitance - 340 - pF
Figure 11
- 950 - pF
reverse transfer capacitance - 230 - pF
turn-on delay time VDD=15V; ID= 55 A; VGS=10V;
=5Ω; resistive load
R
turn-on rise time - 45 80 ns
G
- 8 15 ns
turn-off delay time - 45 80 ns
turn-off fall time - 40 60 ns
source-drain (diode forward)
voltage
IS= 25 A; VGS=0V;Figure 12 - 0.95 1.2 V
=55A;VGS= 0 V - 1.2 - V
I
S
9397 750 08642
Product data Rev. 02 — 2 August 2001 5 of 14
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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