Philips PHB45N03LT, PHD45N03LT, PHP45N03LT Datasheet
Philips Semiconductors Product specification
TrenchMOS transistor PHP45N03LT, PHB45N03LT, PHD45N03LT
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
DSS
= 30 V
• Very low on-state resistance
• Fast switching I
D
= 45 A
• Stable off-state characteristics
• High thermal cycling performance R
DS(ON)
≤ 24 mΩ (VGS = 5 V)
• Low thermal resistance
R
DS(ON)
≤ 21 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The combinationofverylow on-state resistance and low switching losses make this device the optimum choice in high
speed computer motherboard d.c. to d.c. converters.
The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB45N03LT is supplied in the SOT404 surface mounting package.
The PHD45N03LT is supplied in the SOT428 surface mounting package.
PINNING SOT78 (TO220AB) SOT404 SOT428
PIN DESCRIPTION
1 gate
2 drain
1
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
V
DGR
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
V
GS
Gate-source voltage - ± 15 V
V
GSM
Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V
I
D
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 45 A
Tmb = 100 ˚C; VGS = 10 V - 33 A
I
DM
Pulsed drain current Tmb = 25 ˚C - 180 A
P
D
Total power dissipation Tmb = 25 ˚C - 86 W
Tj, T
stg
Operating junction and - 55 175 ˚C
storage temperature
d
g
s
1
2
3
tab
13
tab
2
123
tab
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
June 1998 1 Rev 1.400
Philips Semiconductors Product specification
TrenchMOS transistor PHP45N03LT, PHB45N03LT, PHD45N03LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - - 1.75 K/W
to mounting base
R
th j-a
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
V
GS(TO)
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
R
DS(ON)
Drain-source on-state VGS = 10 V; ID = 25 A - 16 21 mΩ
resistance VGS = 5 V; ID = 25 A - 20 24 mΩ
VGS = 5 V; ID = 25 A; Tj = 175˚C - - 45 mΩ
g
fs
Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S
I
DSS
Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
I
GSS
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Q
g(tot)
Total gate charge ID = 20 A; V
DD
= 24 V; VGS = 10 V - 40 - nC
Q
gs
Gate-source charge - 7 - nC
Q
gd
Gate-drain (Miller) charge - 10 - nC
t
d on
Turn-on delay time VDD = 15 V; ID = 25 A; - 10 20 ns
t
r
Turn-on rise time VGS = 10 V; RG = 5 Ω -5075ns
t
d off
Turn-off delay time Resistive load - 50 75 ns
t
f
Turn-off fall time - 30 45 ns
L
d
Internal drain inductance Measured tab to centre of die - 3.5 - nH
L
d
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF
C
oss
Output capacitance - 270 - pF
C
rss
Feedback capacitance - 140 - pF
June 1998 2 Rev 1.400
Philips Semiconductors Product specification
TrenchMOS transistor PHP45N03LT, PHB45N03LT, PHD45N03LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
Continuous source current - - 45 A
(body diode)
I
SM
Pulsed source current (body - - 180 A
diode)
V
SD
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 40 A; VGS = 0 V - 1.0 -
t
rr
Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 52 - ns
Q
rr
Reverse recovery charge VGS = -10 V; VR = 25 V - 0.08 - µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
W
DSS
Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
D 25 ˚C
= f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
D 25 ˚C
= f(Tmb); conditions: VGS ≥ 5 V
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
June 1998 3 Rev 1.400
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