Philips PHB37N06LT, PHP37N06LT Datasheet

Philips Semiconductors Product specification

TrenchMOS™ transistor		PHP37N06LT, PHB37N06LT, PHD37N06LT
Logic level FET
FEATURES	SYMBOL						QUICK REFERENCE DATA
• 'Trench' technology				d			VDSS = 55 V
• Very low on-state resistance							ID = 37 A
• Fast switching
• Stable off-state characteristics							RDS(ON) ≤ 35 mΩ (VGS = 5 V)
• High thermal cycling performance	g
• Low thermal resistance							RDS(ON) ≤ 32 mΩ (VGS = 10 V)
				s

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.

The PHP37N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB37N06LT is supplied in the SOT404 surface mounting package.

The PHD37N06LT is supplied in the SOT428 surface mounting package.

PINNING

SOT78 (TO220AB) SOT404

SOT428

PIN DESCRIPTION

tab

1gate

2drain1

3source tab drain

1 2 3

	tab		tab
	2		2
1	3	1	3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDSS	Drain-source voltage	Tj = 25 ˚C to 175˚C	-	55	V
VDGR	Drain-gate voltage	Tj = 25 ˚C to 175˚C; RGS = 20 kΩ	-	55	V
VGS	Gate-source voltage		-	± 13	V
ID	Continuous drain current	Tmb = 25 ˚C	-	37	A
		Tmb = 100 ˚C	-	26	A
IDM	Pulsed drain current	Tmb = 25 ˚C	-	148	A
PD	Total power dissipation	Tmb = 25 ˚C	-	100	W
Tj, Tstg	Operating junction and		- 55	175	˚C
	storage temperature

1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

September 1998

1

Rev 1.400

Philips Semiconductors Product specification

TrenchMOS™ transistor

PHP37N06LT, PHB37N06LT, PHD37N06LT

Logic level FET

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

Rth j-mb

Thermal resistance junction

-

1.5

K/W

to mounting base

Rth j-a

Thermal resistance junction

SOT78 package, in free air

60

-

K/W

to ambient

SOT404 and SOT428 packages, pcb

50

-

K/W

mounted, minimum footprint

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VC

Electrostatic discharge

Human body model (100 pF, 1.5 kΩ)

-

2

kV

capacitor voltage, all pins

ELECTRICAL CHARACTERISTICS

Tj= 25˚C

unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V(BR)DSS

Drain-source breakdown

VGS = 0 V; ID = 0.25 mA;

55

-

-

V

voltage

Tj = -55˚C

50

-

-

V

V(BR)GSS

Gate-source breakdown

IG = ±1 mA;

10

-

-

V

voltage

VGS(TO)

Gate threshold voltage

VDS = VGS; ID = 1 mA

1.0

1.5

2.0

V

Tj

= 175˚C

0.5

-

-

V

Tj = -55˚C

-

-

2.3

V

RDS(ON)

Drain-source on-state

VGS = 5 V; ID = 17 A

-

28

35

mΩ

resistance

VGS = 10 V; ID = 17 A

-

26

32

mΩ

gfs

Tj

= 175˚C

-

-

74

mΩ

Forward transconductance

VDS = 25 V; ID = 15 A

12

40

-

S

IGSS

Gate source leakage current

VGS = ±5 V; VDS = 0 V

-

0.02

1

μA

Tj

= 175˚C

-

-

20

μA

IDSS

Zero gate voltage drain

VDS = 55 V; VGS = 0 V;

-

0.05

10

μA

current

Tj

= 175˚C

-

-

500

μA

Qg(tot)

Total gate charge

ID = 30 A; VDD = 44 V; VGS = 5 V

-

22.5

-

nC

Qgs

Gate-source charge

-

6

-

nC

Qgd

Gate-drain (Miller) charge

-

11

-

nC

td on

Turn-on delay time

VDD = 30 V; ID = 25 A;

-

14

21

ns

tr

Turn-on rise time

VGS = 5 V; RG = 10 Ω

-

77

110

ns

td off

Turn-off delay time

Resistive load

-

55

80

ns

tf

Turn-off fall time

-

48

65

ns

Ld

Internal drain inductance

Measured from tab to centre of die

-

3.5

-

nH

Ld

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

-

nH

(SOT78 package only)

Ls

Internal source inductance

Measured from source lead to source

-

7.5

-

nH

bond pad

Ciss

Input capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz

-

1050

1400

pF

Coss

Output capacitance

-

205

245

pF

Crss

Feedback capacitance

-

113

150

pF

September 1998

2

Rev 1.400

Philips Semiconductors Product specification

TrenchMOS™ transistor		PHP37N06LT, PHB37N06LT, PHD37N06LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.			MAX.			UNIT
IS	Continuous source current		-	-			37			A
	(body diode)
ISM	Pulsed source current (body		-	-			148			A
	diode)
VSD	Diode forward voltage	IF = 25 A; VGS = 0 V	-	0.95			1.2			V
		IF = 34 A; VGS = 0 V	-	1.0			-			V
trr	Reverse recovery time	IF = 34 A; -dIF/dt = 100 A/ms;	-	40			-			ns
Qrr	Reverse recovery charge	VGS = -10 V; VR = 30 V	-	0.16			-			mC
AVALANCHE LIMITING VALUE
SYMBOL	PARAMETER	CONDITIONS	MIN.		MAX.				UNIT
WDSS	Drain-source non-repetitive	ID = 20 A; VDD £ 25 V; VGS = 5 V;	-			45				mJ
	unclamped inductive turn-off	RGS = 50 W; Tmb = 25 ˚C
	energy

120	PD%					Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0	0	20	40	60	80	100	120	140	160	180
					Tmb / C
	Fig.1.		Normalised power dissipation.
		PD% = 100×PD/PD 25 ˚C = f(Tmb)

ID%					Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0	20	40	60	80	100	120	140	160	180
				Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100×ID/ID 25 ˚C = f(Tmb); conditions: VGS ³ 5 V

September 1998

3

Rev 1.400