Philips PHB13N40E, PHP13N40E, PHW13N40E Datasheet

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Philips PHB13N40E, PHP13N40E, PHW13N40E Datasheet

Philips Semiconductors Preliminary specification

PowerMOS transistors

 

PHP13N40E, PHB13N40E, PHW13N40E

Avalanche energy rated

 

 

 

 

 

FEATURES

SYMBOL

QUICK REFERENCE DATA

Repetitive Avalanche Rated

Fast switching

Stable off-state characteristics

High thermal cycling performance

Low thermal resistance

d

VDSS = 400 V

ID = 12.8 A

g

RDS(ON) 0.4 Ω

s

GENERAL DESCRIPTION

N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications.

The PHP13N40E is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHW13N40E is supplied in the SOT429 (TO247) conventional leaded package.

The PHB13N40E is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB) SOT404

PIN DESCRIPTION

tab

1gate

2drain1

3source tab drain

1 2 3

 

tab

 

2

1

3

SOT429 (TO247)

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

 

 

 

 

 

 

VDSS

Drain-source voltage

Tj = 25 ˚C to 150˚C

-

400

V

VDGR

Drain-gate voltage

Tj = 25 ˚C to 150˚C; RGS = 20 kΩ

-

400

V

VGS

Gate-source voltage

Tmb = 25 ˚C; VGS = 10 V

-

± 30

V

ID

Continuous drain current

-

12.8

A

 

 

Tmb = 100 ˚C; VGS = 10 V

-

8.1

A

IDM

Pulsed drain current

Tmb = 25 ˚C

-

51

A

PD

Total dissipation

Tmb = 25 ˚C

-

156

W

Tj, Tstg

Operating junction and

 

- 55

150

˚C

 

storage temperature range

 

 

 

 

1 It is not possible to make connection to pin 2 of the SOT404 package.

January 1998

1

Rev 1.000

Philips Semiconductors

Preliminary specification

 

 

PowerMOS transistors

PHP13N40E, PHB13N40E, PHW13N40E

Avalanche energy rated

 

 

 

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

EAS

Non-repetitive avalanche

 

energy

E

Repetitive avalanche energy2

AR

 

IAS, IAR

Repetitive and non-repetitive

 

avalanche current

Unclamped inductive load, ID = 12.8 A;

 

-

666

mJ

VDD 50 V; starting Tj = 25˚C; RGS = 50

Ω;

 

 

 

VGS = 10 V

 

-

16.6

mJ

 

 

 

 

-

12.8

A

 

 

 

 

 

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Rth j-mb

Thermal resistance junction

 

-

-

0.8

K/W

 

to mounting base

 

 

 

 

 

Rth j-a

Thermal resistance junction

SOT78 package, in free air

-

60

-

K/W

 

to ambient

SOT429 package, in free air

-

45

-

K/W

 

 

SOT404 package, pcb mounted, minimum

-

50

-

K/W

 

 

footprint

 

 

 

 

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

V(BR)DSS

Drain-source breakdown

VGS = 0 V; ID = 0.25 mA

400

-

-

V

 

voltage

 

 

 

 

 

V(BR)DSS /

Drain-source breakdown

VDS = VGS; ID = 0.25 mA

-

0.1

-

%/K

Tj

voltage temperature

 

 

 

 

 

 

coefficient

 

 

 

 

Ω

RDS(ON)

Drain-source on resistance

VGS = 10 V; ID = 6.4 A

-

0.35

0.4

VGS(TO)

Gate threshold voltage

VDS = VGS; ID = 0.25 mA

2.0

3.0

4.0

V

gfs

Forward transconductance

VDS = 30 V; ID = 6.4 A

4

8

-

S

IDSS

Drain-source leakage current

VDS = 400 V; VGS = 0 V

-

1

25

μA

IGSS

 

VDS = 320 V; VGS = 0 V; Tj = 125 ˚C

-

50

500

μA

Gate-source leakage current

VGS = ±30 V; VDS = 0 V

-

10

200

nA

Qg(tot)

Total gate charge

ID = 12.8 A; VDD = 320 V; VGS = 10 V

-

125

150

nC

Qgs

Gate-source charge

 

-

10

13

nC

Qgd

Gate-drain (Miller) charge

 

-

68

85

nC

td(on)

Turn-on delay time

VDD = 200 V; RD = 15 Ω;

-

18

-

ns

tr

Turn-on rise time

RG = 5.6 Ω

-

90

-

ns

td(off)

Turn-off delay time

 

-

150

-

ns

tf

Turn-off fall time

 

-

100

-

ns

Ld

Internal drain inductance

Measured from tab to centre of die

-

3.5

-

nH

Ld

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

-

nH

 

 

(SOT78 package only)

 

 

 

 

Ls

Internal source inductance

Measured from source lead to source

-

7.5

-

nH

 

 

bond pad

 

 

 

 

Ciss

Input capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz

-

1400

-

pF

Coss

Output capacitance

 

-

260

-

pF

Crss

Feedback capacitance

 

-

150

-

pF

2 pulse width and repetition rate limited by Tj max.

January 1998

2

Rev 1.000

Philips Semiconductors Preliminary specification

PowerMOS transistors

PHP13N40E, PHB13N40E, PHW13N40E

 

Avalanche energy rated

 

 

 

 

 

 

 

 

 

 

 

 

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

 

 

 

 

 

Tj = 25 ˚C unless otherwise specified

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

IS

Continuous source current

Tmb = 25˚C

-

-

12.8

A

 

 

(body diode)

 

 

 

 

 

 

ISM

Pulsed source current (body

Tmb = 25˚C

-

-

51

A

 

 

diode)

 

 

 

 

 

 

VSD

Diode forward voltage

IS = 12.8 A; VGS = 0 V

-

-

1.2

V

 

trr

Reverse recovery time

IS = 12.8 A; VGS = 0 V; dI/dt = 100 A/μs

-

460

-

ns

 

Qrr

Reverse recovery charge

 

-

6.7

-

μC

 

January 1998

3

Rev 1.000

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