Philips PHB130N03LT, PHP130N03LT Datasheet

Philips Semiconductors Product specification

TrenchMOS™ transistor				PHP130N03LT, PHB130N03LT
Logic level FET
FEATURES	SYMBOL					QUICK REFERENCE DATA
• 'Trench' technology			d			VDSS = 30 V
• Very low on-state resistance						ID = 75 A
• Fast switching
• Stable off-state characteristics						RDS(ON) ≤ 6 mΩ (VGS = 5 V)
• High thermal cycling performance	g
• Low thermal resistance						RDS(ON) ≤ 5 mΩ (VGS = 10 V)
			s

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.

The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB130N03LT is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

PIN DESCRIPTION

tab

1gate

2drain1

3source tab drain

1 2 3

	tab
	2
1	3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDSS	Drain-source voltage	Tj = 25 ˚C to 175˚C	-	30	V
VDGR	Drain-gate voltage	Tj = 25 ˚C to 175˚C; RGS = 20 kΩ	-	30	V
VGS	Gate-source voltage		-	± 13	V
ID	Continuous drain current	Tmb = 25 ˚C; VGS = 5 V	-	75	A
		Tmb = 100 ˚C; VGS = 5 V	-	75	A
IDM	Pulsed drain current	Tmb = 25 ˚C	-	240	A
PD	Total power dissipation	Tmb = 25 ˚C	-	187	W
Tj, Tstg	Operating junction and		- 55	175	˚C
	storage temperature

1 It is not possible to make connection to pin 2 of the SOT404 package.

January 1998

1

Rev 1.300

Philips Semiconductors Product specification

TrenchMOS™ transistor

PHP130N03LT, PHB130N03LT

Logic level FET

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VC

Electrostatic discharge

Human body model (100 pF, 1.5 kΩ)

-

2

kV

capacitor voltage, all pins

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Rth j-mb

Thermal resistance junction

-

-

0.8

K/W

to mounting base

Rth j-a

Thermal resistance junction

SOT78 package, in free air

-

60

-

K/W

to ambient

SOT404 package, pcb mounted, minimum

-

50

-

K/W

footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C

unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V(BR)DSS

Drain-source breakdown

VGS = 0 V; ID = 0.25 mA;

30

-

-

V

voltage

Tj = -55˚C

27

-

-

V

V(BR)GSS

Gate-source breakdown

IG = 1 mA

10

-

-

V

voltage

VGS(TO)

Gate threshold voltage

VDS = VGS; ID = 1 mA

1

1.5

2

V

Tj

= 175˚C

0.5

-

-

V

Tj = -55˚C

-

-

2.3

V

RDS(ON)

Drain-source on-state

VGS = 5 V; ID = 25 A

-

5

6

mΩ

resistance

VGS = 10 V; ID = 25 A

-

4.5

5

mΩ

gfs

VGS = 5 V; ID = 25 A; Tj = 175˚C

-

-

11

mΩ

Forward transconductance

VDS = 25 V; ID = 25 A

20

40

-

S

IGSS

Gate-source leakage current

VGS = ±5 V; VDS = 0 V;

-

0.02

1

μA

Tj

= 175˚C

-

-

10

μA

IDSS

Zero gate voltage drain

VDS = 30 V; VGS = 0 V;

-

0.05

10

μA

current

Tj

= 175˚C

-

-

500

μA

Qg(tot)

Total gate charge

ID = 75 A; VDD = 24 V; VGS = 5 V

-

92

-

nC

Qgs

Gate-source charge

-

10

-

nC

Qgd

Gate-drain (Miller) charge

-

36

-

nC

td on

Turn-on delay time

VDD = 15 V; ID = 25 A;

-

45

60

ns

tr

Turn-on rise time

VGS = 5 V; RG = 5 Ω

-

120

170

ns

td off

Turn-off delay time

Resistive load

-

225

300

ns

tf

Turn-off fall time

-

100

135

ns

Ld

Internal drain inductance

Measured tab to centre of die

-

3.5

-

nH

Ld

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

-

nH

(SOT78 package only)

Ls

Internal source inductance

Measured from source lead to source

-

7.5

-

nH

bond pad

Ciss

Input capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz

-

5000

-

pF

Coss

Output capacitance

-

1150

-

pF

Crss

Feedback capacitance

-

500

-

pF

January 1998

2

Rev 1.300