Philips PHB11N06LT, PHD11N06LT, PHP11N06LT Datasheet

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Philips Semiconductors Product specification

N-channel TrenchMOStransistor

PHP11N06LT, PHB11N06LT

 

Logic level FET

 

 

 

PHD11N06LT

 

 

 

 

 

 

 

 

 

 

 

 

 

FEATURES

SYMBOL

 

 

QUICK REFERENCE DATA

 

 

 

 

 

 

 

'Trench' technology

d

 

 

VDSS = 55 V

 

• Low on-state resistance

 

 

 

ID = 10.5 A

 

• Fast switching

 

 

 

 

• Logic level compatible

 

 

 

RDS(ON) 150 mΩ (VGS = 5 V)

 

 

g

 

 

 

 

s

 

 

RDS(ON) 130 mΩ (VGS = 10 V)

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology.

Applications:-

d.c. to d.c. converters

switched mode power supplies

The PHP11N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB11N06LT is supplied in the SOT404 (D2PAK) surface mounting package.

The PHD11N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING

SOT78 (TO220AB) SOT404 (D2PAK)

SOT428 (DPAK)

PIN DESCRIPTION

tab

1gate

2drain 1

3source

1 2 3

tab drain

 

tab

 

tab

 

2

 

2

1

3

1

3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

 

 

 

 

 

 

VDSS

Drain-source voltage

Tj = 25 ˚C to 175˚C

-

55

V

VDGR

Drain-gate voltage

Tj = 25 ˚C to 175˚C; RGS = 20 kΩ

-

55

V

VGS

Gate-source voltage

 

-

± 15

V

VGSM

Pulsed gate-source voltage

Tj 150˚C

-

± 20

V

ID

Continuous drain current

Tmb = 25 ˚C

-

10.3

A

 

 

Tmb = 100 ˚C

-

7.3

A

IDM

Pulsed drain current

Tmb = 25 ˚C

-

41

A

PD

Total power dissipation

Tmb = 25 ˚C

-

33

W

Tj, Tstg

Operating junction and

 

- 55

175

˚C

 

storage temperature

 

 

 

 

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

August 1999

1

Rev 1.000

Philips Semiconductors Product specification

N-channel TrenchMOStransistor

PHP11N06LT, PHB11N06LT

 

Logic level FET

 

 

 

 

PHD11N06LT

 

 

 

 

 

 

 

 

 

 

 

 

 

AVALANCHE ENERGY LIMITING VALUES

 

 

 

 

 

 

 

 

 

 

 

Limiting values in accordance with the Absolute Maximum System (IEC 134)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

 

 

MIN.

 

MAX.

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

EAS

 

Non-repetitive avalanche

Unclamped inductive load, IAS = 3.3 A;

-

 

25

 

 

 

mJ

 

 

 

energy

tp = 220 μs; Tj prior to avalanche = 25˚C;

 

 

 

 

 

 

 

 

 

 

 

 

VDD 25 V; RGS = 50 Ω; VGS = 5 V; refer to

 

 

 

 

 

 

 

 

 

IAS

 

Peak non-repetitive

fig:15

 

 

-

 

10.3

 

 

A

 

 

 

 

 

 

 

 

 

 

 

avalanche current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

THERMAL RESISTANCES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

 

 

TYP.

 

MAX.

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rth j-mb

 

Thermal resistance junction

 

 

 

-

 

4.5

 

 

 

K/W

 

 

 

to mounting base

 

 

 

 

 

 

 

 

 

 

 

 

Rth j-a

 

Thermal resistance junction

SOT78 package, in free air

 

 

60

 

-

 

 

 

K/W

 

 

 

to ambient

SOT428 and SOT404 package, pcb

50

 

-

 

 

 

K/W

 

 

 

 

mounted, minimum footprint

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

 

 

 

 

Tj= 25˚C

unless otherwise specified

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

 

 

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V(BR)DSS

 

Drain-source breakdown

VGS = 0 V; ID = 0.25 mA;

 

 

55

-

 

-

 

 

V

 

 

 

voltage

 

Tj = -55˚C

50

-

 

-

 

 

V

 

VGS(TO)

 

Gate threshold voltage

VDS = VGS; ID = 1 mA

 

 

1.0

1.5

 

2.0

 

V

 

 

 

 

 

Tj

= 175˚C

0.5

-

 

-

 

 

V

 

 

 

 

 

Tj = -55˚C

-

-

 

2.3

 

V

 

RDS(ON)

 

Drain-source on-state

VGS = 10 V; ID = 5.5 A

 

 

-

100

 

130

 

mΩ

 

 

 

resistance

VGS = 5 V; ID = 5.5 A

 

 

-

120

 

150

 

mΩ

 

 

 

 

 

Tj

= 175˚C

-

250

 

315

 

mΩ

 

gfs

 

Forward transconductance

VDS = 25 V; ID = 5.5 A

 

 

4

7

 

-

 

 

S

 

IGSS

 

Gate source leakage current

VGS = ±5 V; VDS = 0 V

 

 

-

10

 

100

 

nA

 

IDSS

 

Zero gate voltage drain

VDS = 55 V; VGS = 0 V;

 

 

-

0.05

 

10

 

 

μA

 

 

 

current

 

Tj

= 175˚C

-

-

 

500

 

μA

 

Qg(tot)

 

Total gate charge

ID = 10 A; VDD = 44 V; VGS = 5 V

 

 

-

5.2

 

-

 

 

nC

 

Qgs

 

Gate-source charge

 

 

 

-

1.2

 

-

 

 

nC

 

Qgd

 

Gate-drain (Miller) charge

 

 

 

-

3.0

 

-

 

 

nC

 

td on

 

Turn-on delay time

VDD = 30 V; RD = 2.7 Ω;

 

 

-

6

 

16

 

 

ns

 

tr

 

Turn-on rise time

RG = 10 Ω; VGS = 5 V

 

 

-

64

 

80

 

 

ns

 

td off

 

Turn-off delay time

Resistive load

 

 

-

20

 

30

 

 

ns

 

tf

 

Turn-off fall time

 

 

 

-

26

 

40

 

 

ns

 

Ld

 

Internal drain inductance

Measured from tab to centre of die

-

3.5

 

-

 

 

nH

 

Ld

 

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

 

-

 

 

nH

 

 

 

 

(SOT78 package only)

 

 

 

 

 

 

 

 

 

 

 

Ls

 

Internal source inductance

Measured from source lead to source

-

7.5

 

-

 

 

nH

 

 

 

 

bond pad

 

 

 

 

 

 

 

 

 

 

 

Ciss

 

Input capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz

 

-

250

 

330

 

pF

 

Coss

 

Output capacitance

 

 

 

-

55

 

75

 

 

pF

 

Crss

 

Feedback capacitance

 

 

 

-

42

 

55

 

 

pF

 

August 1999

2

Rev 1.000

Philips Semiconductors Product specification

N-channel TrenchMOStransistor

PHP11N06LT, PHB11N06LT

 

Logic level FET

 

 

 

PHD11N06LT

 

 

 

 

 

 

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

 

 

 

 

Tj = 25˚C unless otherwise specified

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

 

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

 

 

 

IS

Continuous source current

 

 

-

-

10.3

A

 

 

(body diode)

 

 

 

 

 

 

 

ISM

Pulsed source current (body

 

 

-

-

41

A

 

 

diode)

 

 

 

 

 

 

 

VSD

Diode forward voltage

IF = 10 A; VGS = 0 V

 

-

1.15

1.5

V

 

trr

Reverse recovery time

IF = 10 A; -dIF/dt = 100 A/μs;

 

-

35

-

ns

 

Qrr

Reverse recovery charge

VGS = 0 V; VR = 30 V

 

-

55

-

nC

 

August 1999

3

Rev 1.000

Philips PHB11N06LT, PHD11N06LT, PHP11N06LT Datasheet

Philips Semiconductors

Product specification

 

 

N-channel TrenchMOStransistor

PHP11N06LT, PHB11N06LT

Logic level FET

PHD11N06LT

 

 

100

Normalised Power Derating, PD (%)

 

 

 

 

 

 

 

 

 

 

90

 

 

 

 

 

 

 

80

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

40

 

 

 

 

 

 

 

30

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

0

25

50

75

100

125

150

175

 

 

Mounting Base temperature, Tmb (C)

 

 

 

Fig.1.

Normalised power dissipation.

 

 

PD% = 100×PD/PD 25 ˚C = f(Tmb)

 

 

Normalised Current Derating, ID (%)

100

90

80

70

60

50

40

30

20

10

0

0

25

50

75

100

125

150

175

 

 

Mounting Base temperature, Tmb (C)

 

 

Fig.2. Normalised continuous drain current.

ID% = 100×ID/ID 25 ˚C = f(Tmb); conditions: VGS ³ 5 V

100

Peak Pulsed Drain Current, IDM (A)

 

 

RDS(on) = VDS/ ID

 

tp = 10 us

10

 

 

100 us

 

D.C.

1

1 ms

 

 

10 ms

 

100 ms

0.1

 

1

10

100

 

Drain-Source Voltage, VDS (V)

 

Fig.3.

Safe operating area. Tmb = 25 ˚C

 

ID & IDM = f(VDS); IDM single pulse; parameter tp

Transient thermal impedance, Zth j-mb (K/W)

10

D = 0.5

 

 

 

 

 

 

0.2

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

 

 

 

 

 

P

tp

D = tp/T

 

0.05

 

 

 

D

 

 

0.02

 

 

 

 

 

 

 

 

single pulse

 

 

T

 

 

0.1

 

 

 

 

 

 

 

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

 

 

Pulse width, tp (s)

 

 

 

 

Fig.4. Transient thermal impedance.

 

Zth j-mb = f(t); parameter D = tp/T

 

15

Drain Current, ID (A)

 

 

 

 

 

14

Tj = 25 C

VGS = 10V

5 V

13

 

 

 

12

 

 

 

11

 

 

 

10

 

 

 

9

 

 

3.4 V

8

 

 

 

 

 

7

 

 

3.2 V

6

 

 

5

 

 

3 V

4

 

 

 

 

2.8 V

3

 

 

 

 

2.6 V

2

 

 

1

 

 

2.4 V

0

 

 

 

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

 

 

 

Drain-Source Voltage, VDS (V)

 

 

 

Fig.5. Typical output characteristics, Tj = 25 ˚C.

 

 

 

 

ID = f(VDS)

 

 

 

 

Drain-Source On Resistance, RDS(on) (Ohms)

 

 

 

0.5

 

 

2.8V

 

 

 

 

 

Tj = 25 C

 

0.45

 

2.6 V

 

 

 

 

 

 

2.4 V

 

 

 

3 V

 

 

 

 

 

 

0.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.35

 

 

 

 

 

3.2 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.3

 

 

 

 

 

 

 

3.4 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

 

 

 

 

 

 

 

 

 

 

 

0.2

 

 

 

 

 

 

 

 

 

5 V

 

0.15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

 

 

 

 

 

0.05

 

 

 

 

 

 

 

 

VGS = 10V

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

8

9

10

11

 

 

 

Drain Current, ID (A)

 

 

 

 

Fig.6.

Typical on-state resistance, Tj = 25 ˚C.

 

 

 

 

RDS(ON) = f(ID)

 

 

 

 

August 1999

4

Rev 1.000

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