Philips PH3830L User Manual
M3D748
1. Product profile
1.1 Description
1.2 Features
1.3 Applications
PH3830L
N-channel TrenchMOS™ logic level FET
Rev. 03 — 2 March 2004 Product data
N-channel enhancement mode field-effect powertransistorinaplasticpackage using
TrenchMOS™ technology.
■ Low thermal resistance ■ SO8 equivalent area footprint
■ Logic level gate drive ■ Low on-state resistance.
■ DC-to-DC converters ■ Switched-mode power supplies
■ Portable appliances ■ Notebook computers.
1.4 Quick reference data
■ VDS≤ 30 V ■ ID≤ 98 A
■ P
≤ 62.5 W ■ R
tot
DSon
2. Pinning information
Table 1: Pinning - SOT669 (LFPAK), simplified outline and symbol
Pin Description Simplified outline Symbol
1,2,3 source (s)
4 gate (g)
mb mounting base;
connected to drain (d)
1
23mb4
Top view
SOT669 (LFPAK)
MBL286
≤ 3.8 mΩ
MBB076
d
g
s
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
PH3830L LFPAK Plastic single-ended surface mounted package; 4 leads SOT669
4. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
Avalanche ruggedness
E
DS(AL)S
drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V
gate-source voltage - ±20 V
drain current (DC) Tmb=25°C; VGS=10V;Figure 2 and 3 -98A
= 100 °C; VGS=10V;Figure 2 -62A
T
mb
peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; Figure 3 - 290 A
total power dissipation Tmb=25°C; Figure 1 - 62.5 W
storage temperature −55 +150 °C
junction temperature −55 +150 °C
source (diode forward) current (DC) Tmb=25°C - 52 A
peak source (diode forward) current Tmb=25°C; pulsed; tp≤ 10 µs - 150 A
non-repetitive drain-source
avalanche energy
unclamped inductive load; ID= 70.7 A;
= 0.1 ms; VDD≤ 30 V; VGS=10V;
t
p
starting T
=25°C
j
- 250 mJ
9397 750 12945
Product data Rev. 03 — 2 March 2004 2 of 12
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
120
P
der
(%)
80
40
0
0 50 100 150 200
P
P
der
tot
-----------------------
P
tot 25 C°()
100%×=
03aa15
Tmb (°C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
120
I
der
(%)
80
40
0
0 50 100 150 200
03aa23
Tmb (°C)
VGS≥ 10 V
I
I
der
D
-------------------
I
°
D25C
()
100%×=
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
µ
003aaa377
s
VDS (V)
10
I
D
(A)
10
10
1
10
3
Limit R
2
-1
-1
10
DSon
= V
/ I
DS
D
tp = 10 µs
100
1 ms
DC
1 10 10
10 ms
100 ms
Tmb=25°C; IDM is single pulse; VGS=10V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
2
9397 750 12945
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 03 — 2 March 2004 3 of 12
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to mounting base Figure 4 --2K/W
5.1 Transient thermal impedance
003aaa378
δ =
t
p
T
tp (s)
Z
th(j-mb)
(K/W)
10
1
10
δ = 0.5
0.2
0.1
0.02
0.05
single pulse
-1
-4
10
-3
10
-2
10
-1
10
P
1 10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
t
p
T
t
9397 750 12945
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 03 — 2 March 2004 4 of 12
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