Philips PEMD13, PUMD13 User Guide
DATA SH EET
Product specification
Supersedes data of 2001 Feb 27
2003 Oct 08
DISCRETE SEMICONDUCTORS
PEMD13; PUMD13
NPN/PNP resistor-equipped
transistors; R1 = 4.7 kΩ,R2=47kΩ
查询PUMD13供应商
2003 Oct 08 2
Philips Semiconductors Product specification
NPN/PNP resistor-equipped transistors;
R1 = 4.7 kΩ, R2 = 47 kΩ
PEMD13; PUMD13
FEATURES
• Built-in bias resistors
• Simplified circuit design
• Reduction of component count
• Reduced pick and place costs.
APPLICATIONS
• Low current peripheral driver
• Replacement of general purpose transistors in digital
applications
• Control of IC inputs.
QUICK REFERENCE DATA
DESCRIPTION
NPN/PNP resistor-equipped transistors (see “Simplified
outline, symbol and pinning” for package details).
SYMBOL PARAMETER TYP. MAX. UNIT
V
CEO
collector-emitter
voltage
− 50 V
I
O
output current (DC) − 100 mA
TR1 NPN −−−
TR2 PNP −−−
R1 bias resistor 4.7 − kΩ
R2 bias resistor 47 − kΩ
PRODUCT OVERVIEW
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
TYPE
NUMBER
PACKAGE
MARKING CODE
PNP/PNP
COMPLEMENT
NPN/NPN
COMPLEMENT
PHILIPS EIAJ
PEMD13 SOT666 Z1 PEMB13 PEMH13
PUMD13 SOT363 SC-88 3*1
(1)
PUMB13 PUMH13
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
TYPE NUMBER SIMPLIFIED OUTLINE AND SYMBOL
PINNING
PIN DESCRIPTION
PEMD13 1 emitter TR1
PUMD13 2 base TR1
3 collector TR2
4 emitter TR2
5 base TR2
6 collector TR1
123
46
5
Top view
654
123
R2
TR1
TR2
R1
R1 R2
MAM468
2003 Oct 08 3
Philips Semiconductors Product specification
NPN/PNP resistor-equipped transistors;
R1 = 4.7 kΩ, R2 = 47 kΩ
PEMD13; PUMD13
ORDERING INFORMATION
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. Device mounted on an FR4 printed-circuit board, single-sided copper, standard footprint.
2. Reflow soldering is the only recommended soldering method.
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PEMD13 − plastic surface mounted package; 6 leads SOT666
PUMD13 − plastic surface mounted package; 6 leads SOT363
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per transistor; for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter − 50 V
V
CEO
collector-emitter voltage open base − 50 V
V
EBO
emitter-base voltage open collector − 10 V
V
I
input voltage TR1
positive − +30 V
negative −−5V
V
I
input voltage TR2
positive − +5 V
negative −−30 V
I
O
output current (DC) − 100 mA
I
CM
peak collector current − 100 mA
P
tot
total power dissipation T
amb
≤ 25 °C
SOT363 note 1 − 200 mW
SOT666 notes 1 and 2 − 200 mW
T
stg
storage temperature −65 +150 °C
T
j
junction temperature − 150 °C
T
amb
operating ambient temperature −65 +150 °C
Per device
P
tot
total power dissipation T
amb
≤ 25 °C
SOT363 note 1 − 300 mW
SOT666 notes 1 and 2 − 300 mW
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