Philips PDTA114EU Datasheet

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Philips PDTA114EU Datasheet

DISCRETE SEMICONDUCTORS

DATA SHEET

book, halfpage

M3D102

PDTA114EU

PNP resistor-equipped transistor

Product specification

 

1999 Apr 13

Supersedes data of 1998 May 18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Philips Semiconductors

Product specification

 

 

PNP resistor-equipped transistor

PDTA114EU

 

 

 

 

FEATURES

 

 

Built-in bias resistors R1 and R2

 

 

 

(typ. 10 kΩ each)

handbook, 4 columns

3

Simplification of circuit design

 

 

3

Reduces number of components

 

R1

 

and board space.

 

1

 

 

 

 

 

 

R2

APPLICATIONS

 

2

Especially suitable for space

1

2

Top view

 

 

reduction in interface and driver

MAM135

 

 

 

 

circuits

 

 

Inverter circuit configurations

Fig.1

Simplified outline (SOT323) and symbol.

 

without use of external resistors.

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

MARKING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PNP resistor-equipped transistor in a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MARKING

SOT323 plastic package.

 

 

 

 

 

 

 

 

TYPE NUMBER

 

 

 

 

 

 

 

 

CODE(1)

NPN complement: PDTC114EU.

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

3

 

 

 

PINNING

 

 

 

 

 

 

 

PDTA114EU

03

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

 

 

 

2

 

 

 

 

 

 

MGA893 - 1

 

 

 

1. = - : Made in Hong Kong.

PIN

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= t : Made in Malaysia.

 

 

 

 

 

 

 

 

 

 

1

base/input

 

Fig.2 Equivalent inverter

 

 

 

 

 

 

 

 

 

 

2

emitter/ground (+)

 

 

 

 

symbol.

 

 

 

 

 

 

 

 

 

 

 

 

 

3

collector/output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1999 Apr 13

2

Philips Semiconductors

 

 

Product specification

 

 

 

 

 

 

PNP resistor-equipped transistor

 

PDTA114EU

 

 

 

 

 

 

LIMITING VALUES

 

 

 

 

In accordance with the Absolute Maximum Rating System (IEC 134).

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

 

 

 

 

 

 

VCBO

collector-base voltage

open emitter

50

V

VCEO

collector-emitter voltage

open base

50

V

VEBO

emitter-base voltage

open collector

10

V

VI

input voltage

 

 

 

 

 

positive

 

10

V

 

negative

 

40

V

 

 

 

 

 

 

IO

output current (DC)

 

100

mA

ICM

peak collector current

 

100

mA

Ptot

total power dissipation

Tamb 25 °C; note 1

200

mW

Tstg

storage temperature

 

65

+150

°C

Tj

junction temperature

 

150

°C

Tamb

operating ambient temperature

 

65

+150

°C

Note

1. Transistor mounted on an FR4 printed-circuit board.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

 

 

 

 

 

Rth j-a

thermal resistance from junction to ambient

note 1

625

K/W

Note

 

 

 

 

1. Transistor mounted on an FR4 printed-circuit board.

CHARACTERISTICS

Tamb = 25 °C unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

ICBO

collector cut-off current

IE = 0; VCB = 50 V

100

nA

ICEO

collector cut-off current

IB = 0; VCE = 30 V

1

μA

 

 

IB = 0; VCE = 30 V; Tj = 150 °C

50

μA

IEBO

emitter cut-off current

IC = 0; VEB = 5 V

400

μA

hFE

DC current gain

IC = 5 mA; VCE = 5 V

30

 

VCEsat

collector-emitter saturation voltage

IC = 10 mA; IB = 0.5 mA

150

mV

Vi(off)

input-off voltage

IC = 100 μA; VCE = 5 V

1.1

0.8

V

Vi(on)

input-on voltage

IC = 10 mA; VCE = 0.3 V

2.5

1.8

V

R1

input resistor

 

7

10

13

kΩ

 

 

 

 

 

 

 

R2

resistor ratio

 

0.8

1

1.2

 

-------

 

 

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

Cc

collector capacitance

IE = ie = 0; VCB = 10 V; f = 1 MHz

3

pF

1999 Apr 13

3

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