Philips PDIUSBD12 User Manual

Philips Semiconductors

Interconnectivity

PDIUSBD12 Evaluation Board (PC Kit)

1 September 1998

User’s Manual

Rev. 2.1

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Page 2 of 14

PDIUSBD12 Evaluation Board (PC Kit) User’s Manual Rev. 2.1

This is a legal agreement between you (either an individual or an entity) and Philips Semiconductors.
By accepting this product, you indicate your agreement to the disclaimer specified as follows:

DISCLAIMER

PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. THE PRODUCT IS PROVIDED
“AS IS” WITHOUT WARRANTY OF ANY KIND. TO THE MAXIMUM EXTENT
PERMITTED BY APPLICABLE LAW, PHILIPS SEMICONDUCTORS FURTHER
DISCLAIMS ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANT ABILITY, FITNESS FOR A PARTICULAR
PURPOSE, AND NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT OF THE
USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS
WITH THE RECIPIENT. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS
SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL, INCIDENTAL, DIRECT,
INDIRECT, SPECIAL, PUNITIVE, OR OTHER DAMAGES WHATSOEVER
(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
OTHER PECUNIARY LOSS) ARISING OUT OF THIS AGREEMENT OR THE USE OF
OR INABILITY TO USE THE PRODUCT, EVEN IF PHILIPS SEMICONDUCTORS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

TABLE OF CONTENTS

DISCLAIMER .............................................................................................................2

TABLE OF CONTENTS.............................................................................................3

INSTALLATION OF PDIUSBD12 EVALUATION BOARD........................................4

Introduction....................................................................................................................................................4

System Requirements .....................................................................................................................................4

Installation......................................................................................................................................................5

Jumper’s setting on PDIUSBD12 ISA bridging board................................................................................... 5

Location of key components on the PDIUSBD12 evaluation board. ..............................................................6

Installation of firmware, INF and driver........................................................................................................ 7

Using the Host Applet ....................................................................................................................................7

HARDWARE DESCRIPTION.....................................................................................9

Block Diagram................................................................................................................................................9

I/O Mapping................................................................................................................................................... 9

Connectors....................................................................................................................................................10

PAL Equations.............................................................................................................................................11

Address and command decoder...................................................................................................................11

Schematics....................................................................................................................................................12

Schematics for PDIUSBD12 evaluation board ............................................................................................12

Schematic for PDIUSBD12 ISA bridging board..........................................................................................13

Bill of Materials............................................................................................................................................14

Bill of materials of the PDIUSBD12 evaluation board.................................................................................14

Bill of materials of the PDIUSBD12 ISA bridging board.............................................................................14

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

INSTALLATION OF PDIUSBD12 EVALUATION BOARD

Introduction

The PDIUSBD12 evaluation kit uses 2 PC as a complete USB development environment, a host PC
with USB host capability and a device PC running PDIUSBD12’s firmware. The PDIUSBD12 ISA
bridging board is plugged inside the device PC and connects to the evaluation board using a 25-wire
cable. So the device PC behaves as a big USB device.

Features evaluation of PDIUSBD12, firmware and product prototype development can be easily done
with this setup, without the resource limitation of a micro-controller. Customers can also connect the
evaluation board to their own CPU and bus through the 25-wire cable for final product development.
The firmware is carefully developed for high rate data transmission and is written in C, that supports
Borland Turbo C for x86 and Keil C51 for 8031 currently. Supporting to other CPU platforms will be
available soon.

System Requirements

1. PDIUSBD12 evaluation board and ISA bridging board;

2. 25-wire shielding data switch cable;

3. Host PC with USB motherboard or add-on card;

4. Microsoft Windows 98 or Windows NT 5.0 Beta 2;

5. Device PC running Microsoft DOS 6.x;

6. PDIUSBD12 evaluation diskette.
For firmware development:

1. X86 CPU platform: Borland Turbo C++ 3.0 or above;

2. 8031: Keil C51 4.0 or above.

PDIUSBD12 Evaluation Disk

D12FW.EXE

25-Wire Cable

D12TEST.EXE

D12TEST.SYS

D12TEST.INF

USB Cable

D12

Device PC with PDIUSBD12 ISA Bridging Board

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Host PC with USB host Controller

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Page 5 of 14

PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Installation

Jumper’s setting on PDIUSBD12 ISA bridging board

The PDIUSBD12 ISA bridging board is plugged inside the device PC. It will occupy I/O, IRQ and DMA
resources of the device PC. To avoid possible conflicts in settings, we suggest removal of all the
unnecessary cards from the device PC. Sound card and network card may cause conflict in IRQ and
DMA setting.

J2

JP5 JP6

S1

1 8

JP1 JP2 JP3 JP4

Switch S1 sets the base I/O address for the D12 evaluation board. Default base address is 0x368.
The D12 evaluation board occupies 8 I/O locations. A0 to A2 are decoded on the D12 evaluation
board. Switch S1 sets the address decoding of A3 to A9. Please notice that a switch ‘ON’ is logic ‘0’.

SW(n) 1 2 3 4 5 6 7 8
Address X A3 A4 A5 A6 A7 A8 A9
Default OFF OFF ON OFF OFF ON OFF OFF

Jumpers JP1 and JP2 set the IRQ number for the D12 evaluation board. Default setting is IRQ5 or
JP1 is shorted.

IRQ Number IRQ5 IRQ7
Jumper’s Setting JP1 JP2
Default ON OFF

Jumpers JP3 to JP6 set the DMA number for the D12 evaluation board. Default setting is DMA3 or
JP4 and JP6 are shorted. Please note that a respective pair of jumpers is needed to set a particular
DMA channel.

DMA Number DMA1 DMA3
Jumper’s Setting JP3, JP5 JP4, JP6
Default OFF, OFF ON, ON

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Possible conflict table:

IRQ or DMA

Possible Conflict
Number
IRQ5 Creative SoundBlaster™ and compatible sound cards always occupy

this IRQ by default. If this kind of sound card is installed, you should

check its settings or remove it.

Some network cards may also use this IRQ.
IRQ7 Used by parallel port by default. May cause printing problem on

device PC.
DMA1 Creative SoundBlaster™ and compatible sound cards always occupy

this DMA by default. If this kind of sound card is installed, you should

check its settings or remove it.
DMA3 No conflict.

Location of key components on the PDIUSBD12 evaluation board.

J1

D1

J2

J3

See the table below for the list of connectors.

Connector Descriptions
J1 USB upstream connector
J2 DB25 data bus connector
J3 Extension board connector

See the table below for the list of switch and LEDs.

Name Descriptions
S1, S2, S3, S4 Test switches
D1
D2, D3, D4, D5 Test LEDs

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S1

S2S3S4

GoodLink™ LED

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D5 D4 D3 D2

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Page 7 of 14

PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Installation of firmware, INF and driver

The firmware, D12FW.EXE, runs on the device PC under DOS mode. When D12FW starts, it lights up
test LEDs on the evaluation board for 1 second. This means that the I/O address setting is correct.
And the evaluation board is disconnected and re-connected to USB by SoftConnectTM. If this is the
first time that the evaluation board is connected to host PC, host OS Device Manager will prompt
installation of INF and driver. Select the location of D12TEST.INF and D12TEST.SYS and complete
installation procedure.

Some useful key command is supported when the firmware is running.

Key Operation
ESC Disconnect USB and quit PDIUSBD12 firmware.
ENTER
i Display firmware status information.
v Switch on/off verbose mode, normally turned off for faster operation.

Using the Host Applet

Reconnect USB using SoftConnectTM.

The test applet, D12TEST.EXE, exercises all PDIUSBD12 endpoints. Testing of control endpoints can
be further done by standard USB Chapter 9 test programs.

The operation of each endpoint is designed according to its nature that is supported in PDIUSBD12.
Generic in and generic out endpoints has max packet size of 16 bytes and supports I/O access only.
So they are suitable for small size and low rate data transfer like keyboard and logic controls. The
main endpoints have max packet size of 64 bytes or 128 bytes with double buffering and DMA
support. So they are suitable for high data rate, large size data transfer.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

See the table below for the description of endpoints operations on PDIUSBD12 evaluation board.

Endpoint
Number
1 GenericInThis pipe is defined as Interrupt In pipe. The PDIUSBD12 evaluation

1 Generic

2 Main In

Main endpoints support 3 different test modes:

1. Scan mode: The PDIUSBD12 evaluation board acts like a scanner. It sends data packets to the
host PC as fast as possible. This mode is used to evaluate the maximal Bulk In transfer rate.

2. Print mode: The PDIUSBD12 evaluation board acts like a printer. It receives data packets from
the host PC as fast as possible. This mode is used to evaluate the maximal Bulk Out transfer rate.

3. Loop back mode: In this mode, the PDIUSBD12 evaluation board receives data packets on Main
Out endpoint and sends them back to the host PC on Main In endpoint. This mode is used to test
the data integrity of transfers.

The “Buffer Size” setting on the test applet is determined by the firmware and hardware ability of the
evaluation board. For PC kit, the maximal size is limited to 64000; On USB-EPP kit, this is limited to

16384.

Endpoint
Type

Out

Main Out

Operations

board sends key press/release data packet to the host when test keys
are pressed or released. The firmware uses I/O accesses on this
endpoint.
This pipe is defined as Interrupt Out pipe. Data packet received from
host is interpreted as LED control and the D12 evaluation board
firmware will light up the corresponding LED. The firmware uses I/O
accesses on this endpoint.
These pipes are defined as Bulk In/Out endpoints. Test applet and the
PDIUSBD12 evaluation board supports 3 test modes: loop-back mode,
print mode and scan mode. The firmware uses DMA for data transfer
on these endpoints.

The “Repeat Times” for loop-back test controls the numbers of iterations of loop-back, which is useful
for debugging. “-1” means it is infinite.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

HARDWARE DESCRIPTION

On USB host side, a

sample application program

D12TEST.EXE and a

general purpose minidriver

D12TEST.SYS are

provided.

USB Host PC

D12 Sample Applet

D12TEST.EXE

D12 Sample Driver

D12TEST.SYS

USBD

USB Host Controller

Driver

USB Host Controller

System Block

Diagram of D12

Evaluation Kit

25 Pin Interface

1. VCC, GND

2. D0 - D7

3. ADDRESS ENABLE

4. IOW, IOR, IRQ, RESET

5. DREQ, DACK, EOT

D12 Evaluation Board

Test

Key

Test
LED

General

Input port

General

Output port

PDIUSBD12

On device side, sample firmware

D12FW.EXE is provided for

running on device PC. The
firmware is written in C for easily
portable to other CPU platforms.

Command

and Address

Decoder

Bi-direction

Bus

Transceiver

Pin

Customer's System

25

Pin

I/F

CPU,

Memory,
and DMA
Controller

USB Device PC

25
I/F

D12 ISA Bridging Board

25

Pin

I/F

DIP

Switches

and

Jumpers

ISA
Slot

Block Diagram

Above block diagram shows 5 main components on the PDIUSBD12 evaluation board. Beside bus
transceiver, address/command decoder and PDIUSBD12, a general input port and a general output
port are included in the design. These input and output ports are designed for test purposes, such as
test switches and test LEDs. They also act as glue logic to adapt the PDIUSBD12 to the ISA bus. For
example, ISA interrupt is edge triggered, but PDIUSBD12 interrupt is level triggered. The MSB of the
general output port is used as interrupt enable to convert level triggered interrupt to edge triggered.

I/O Mapping

PDIUSBD12 evaluation board uses 8 I/O addresses:

Offset Usage
0 D12 data register, R/W
1 D12 command register, W only
2 General input port, R only
3 General output port, W only
4 to 7 Reserved for expansion board

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Bit description for general input port:

Bit Usage
0 Key S1, ‘0’ for pressed
1 Key S2, ‘0’ for pressed
2 Key S3, ‘0’ for pressed
3 Key S4, ‘0’ for pressed
4
5 USB bus power state, ‘1’ for USB VBUS present
6 D12 SUSPEND pin state
7 D12 INT_N pin state

Bit description for general output port:

Bit Usage
0 LED D2, ‘1’ lights up LED
1 LED D3, ‘1’ lights up LED
2 LED D4, ‘1’ lights up LED
3 LED D5, ‘1’ lights up LED
4 Reserved
5 Reserved
6 Suspend control, ‘1’ forces D12 SUSPEND pin low
7 Interrupt enable, ‘1’ enables interrupt

D12 GoodLinkTM pin state

Connectors

25 wire connector for PDIUSBD12 evaluation board:

Pin Type Description
1 POWER VCC
2 POWER GND
3 I/O DATA7
4 I/O Zero Wait State
5 I/O DATA6
6 I/O Reserved
7 I/O DATA5
8 O CLKOUT: This line is connected to PDIUSBD12 CLKOUT pin.
9 I/O DATA4
10 I -AD_EN: This line is the decoder output for address decoding A3 to

A9. This signal is active low when PDIUSBD12 evaluation board I/O

address is selected.
11 I/O DATA3
12 I RESET: This line is used to reset or initialize system logic upon

power-up and is active high.
13 I/O DATA2
14 I -IOW: This command line instructs an I/O device to read the data on

the data bus. It may be driven by the processor or the DMA controller.

This signal is active low.
15 I/O DATA1
16 I -IOR: This command line instructs an I/O device to drive its data onto

the data bus. It may be driven by the processor or the DMA controller.

This signal is active low.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

17 I/O DATA0
18 I T/C, Terminal Count: This line provides a pulse when terminal count

for any DMA channel is reached. This signal is active high.
19 I ADDR2
20 I -DACK: This line is used to acknowledge DMA request and is active

low.
21 I ADDR1
22 O DRQ: This line is asynchronous channel request used by peripheral

devices to gain DMA service. A DMA request is generated by bringing

DRQ line to an active high.
23 I ADDR0
24 O IRQ: This line is raising edge triggered. An interrupt request is

generated by raising this line high and hold until it is acknowledged by

the processor.
25 POWER GND

PAL Equations

Address and command decoder

/** Inputs **/
Pin 1 = ADDR2;

Pin 2 = ADDR1;
Pin 3 = ADDR0;
Pin 4 = !IOW;
Pin 5 = !IOR;
Pin 6 = !DACK;
Pin 7 = !AD_EN;
Pin 8 = RESET;
Pin 9 = INT_N;
Pin 11 = INT_EN;

/** Outputs **/
Pin 12 = IRQ;

Pin 13 = RESET_N;
Pin 14 = RD_N;
Pin 15 = WAIT;
Pin 16 = !CS_D12;
Pin 17 = !WR_273;
Pin 18 = !RD_244;
Pin 19 = !DIR_245;

/** Logic Equations **/
!DIR_245 = (!AD_EN & !DACK) # !IOR # RESET;

!RD_244 = !AD_EN # !(!ADDR2 & ADDR1 & !ADDR0) # !IOR;
!WR_273 = !AD_EN # !(!ADDR2 & ADDR1 & ADDR0) # !IOW;
!CS_D12 = !AD_EN # !(!ADDR2 & !ADDR1) # (!IOW & !IOR);
RESET_N = !RESET;
IRQ = !INT_N & INT_EN;
WAIT.OE = CS_D12;
WAIT = RESET;
RD_N = !IOR;

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Schematics

Schematics for PDIUSBD12 evaluation board

C15
1000P

C1

VCC VCC

4.7 TANT

+

J2

DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0

ADDR2
ADDR1
ADDR0

DATA[0..7]

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

ADDR2
ADDR1
ADDR0

-IOW

-IOR

-DACK

-AD_EN
RESET

VCC

INT_EN
INT_N

D7
D6
D5
D4
D3
D2
D1
D0

J3
CON20A

2
3
4
5
6
7
8
9

19

1

1
2
3
4
5
6
7
8
9

11

DB25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Shell to GND

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

G
DIR

I1

O1

I2

O2

I3

O3

I4

O4

I5

O5

I6

O6

I7

O7

I8

O8
I9
I10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CLKOUT

-AD_EN
RESET

-IOW

-IOR
T/C

-DACK
DRQ
IRQ

18

D0

17

D1

16

D2

15

D3

14

D4

13

D5

12

D6

11

D7

U2
74LS245

-DIR_245

19
18

-RD_EVAL

17

-WR_EVAL

16

-CS_D12

15

ZERO_WAIT

14
13

RESET_N

12

IRQ

U5
16L8

CLKOUT

INT_N

RESET_N

-AD_EN

-IOW

-IOR
ADDR2
ADDR1
ADDR0

R4

R5

4.7K

4.7K

VCC

D[0..7]

C9

C8

0.1

0.1

C10

0.1

-CS_D12
SUSPEND

INT_N

D0
D1
D2
D3
D4
D5
D6
D7

C11

0.1

C13

470P, Ceramic

U1

1

D0

2

D1

3

D2

4

D3

5
6

D4

7

D5

8

D6

9

D7

10
11
12
13
14

18

D0

16

D1

14

D2

12

D3

9

D4

7

D5

5

D8D6

3

D7

U3
74HCT244

3
4
7

8
13
14
17
18

11

1

U6
74HCT273

C12

0.1

V_BUS

DATA0
DATA1
DATA2
DATA3
GND
DATA4
DATA5
DATA6
DATA7
ALE
CS_N
SUSPEND
CLKOUT
INT_N

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

D1
D2
D3
D4
D5
D6
D7
D8

CLK
CLR

S5

BUS POWERED

PDIUSBD12

A0

VOUT3.3

D+

D-

VCC
XTAL2
XTAL1

GL_N

RESET_N

EOT_N

DMACK_N

DMREQ

WR_N

RD_N

2

1A1

4

1A2

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

2

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

Q8

VCC

+

C7
10 TANT

R1
470

D1
GREEN

28

ADDR0

27
26
25
24
23

XTAL2

22

XTAL1

21
20
19
18

-DACK

17

DRQ

16

-IOW

15

-IOR

1 2

U4A
74LS05

13 12

U4F
74LS05

Title

D12 EVALUATION BOARD

Size Document Number Rev

D12-EVAL-200 2.00

A

Date: Sheet of

C3

+

0.1

R2
22 1%

6MHz

Y1

C5
47P

R3
22 1%

C6
22P

OSC1

5

G4O

1

8

N

V

V_BUS

* OSC1 is optional replacement
for Y1, C5 and C6.

R11
1K

R16
1M

3 4

V_BUS

C2

4.7 TANT

R7
10KR810KR910K

VCC

U4B
74LS05

5 6

U4D
74LS05

L1
Ferrite Bead

L2

Ferrite Bead

C16

0.1

R12
470

D2
RED

U4C
74LS05

9 8

R10
10K

R13
470

D3
RED

11 10

1 1Thursday, April 23, 1998

C14

0.1

D4
RED

U4E
74LS05

1
2
3
4
5

R14
470

J1

VBUS
D­D+
GND
SHIELD

UP_CONN

VCC

VCC

R15
470

D5
RED

S1
S2
S3
S4

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Schematic for PDIUSBD12 ISA bridging board

J2

VCC

DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR2
ADDR1
ADDR0

IRQ5
IRQ7

DRQ1
DRQ3

-DACK1

-DACK3

DB25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Shell to GND

+

C3

4.7u

ZERO_WAIT

-AD_EN
RESET

-IOW

-IOR
T/C

-DACK
DRQ

C5

0.1

VCC

R1
10K

IRQ

JP1
JP2

JP3
JP4
JP5
JP6

J1

GND
RESET
+5V

IRQ2

-5V
DRQ2

-12V
+12V

GND

-MEMW

-MEMR

-IOW

-IOR

-DACK3
DRQ3

-DACK1
DRQ1

-DACK0
CLOCK

IRQ7

IRQ6

IRQ5

IRQ4
IRQ3

-DACK2

T/C

ALE
+5V
OSC

GND

C2

4.7u

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

CON AT62

C4

0.1

VCC

ZERO_WAIT

VCC

VCC VCC

+

I/O CH CK

A1

DATA7 DATA7

A2

DATA6

A3

DATA5

A4

DATA4

A5

DATA3

A6

DATA2

A7

DATA1

A8

DATA0

A9

I/O CH RDY

A10

AEN

A11

ADDR19

A12

ADDR18

A13

ADDR17

A14

ADDR16

A15

ADDR15

A16

ADDR14

A17

ADDR13

A18

ADDR12

A19

ADDR11

A20

ADDR10

A21

ADDR9

A22

ADDR8

A23

ADDR7

A24

ADDR6

A25

ADDR5

A26

ADDR4

A27

ADDR3

A28

ADDR2

A29

ADDR1

A30

ADDR0

A31

S1
SW DIP-8

8
7
6
5
4
3
2
1

ADDR[0..2]

DATA[0..7]

VCC

9
10
11
12
13
14
15
16

RP1
20K

C

112233445566778

1

18
16
14
12

9
7
5
3

17
15
13
11

8
6
4
2

U1

G
Q7

Q6
Q5
Q4
Q3
Q2
Q1
Q0

P7
P6
P5
P4
P3
P2
P1
P0

74HCT688

P=Q

VCC

C1

0.1

19

-AD_EN

Title

D12 ISA BRIDGING BOARD

Size Document Number Rev

D12-ISA-200 2.00

A

Date: Sheet of

1 1Tuesday, February 24, 1998

_______________________________________________________________________________________________

Philips Semiconductors - Asia Product Innovation Centre

Visit http://www.flexiusb.com

Interconnectivity

Page 14 of 14

PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1

Bill of Materials

Bill of materials of the PDIUSBD12 evaluation board

Item Quantity Reference Part
1 2 C2,C1 4.7 TANT
2 8 C3,C8,C9,C10,C11,C12,C14,C16 0.1
3 1 C5 47P
4 1 C6 22P
5 1 C7 10 TANT
6 1 C13 470P, Ceramic
7 1 C15 1000P
8 1 D1 GREEN
9 4 D2,D3,D4,D5 RED
10 1 J1 UP_CONN
11 1 J2 DB25
12 1 J3 CON20A
13 2 L1,L2 Ferrite Bead
14 1 OSC1 Crystal Oscillator
15 5 R1,R12,R13,R14,R15 470
16 2 R2,R3 22 1%
17 2 R4,R5 4.7K
18 4 R7,R8,R9,R10 10K
19 1 R11 1K
20 1 R16 1M
21 4 S1,S2,S3,S4 SW PUSHBUTTON
22 1 S5 BUS POWERED
23 1 U1 PDIUSBD12
24 1 U2 74LS245
25 1 U3 74HCT244
26 1 U4 74LS05
27 1 U5 16L8
28 1 U6 74HCT273
29 1 Y1 6MHz

Bill of materials of the PDIUSBD12 ISA bridging board

Item Quantity Reference Part
1 3 C1,C4,C5 0.1
2 2 C2,C3 4.7u
3 6 JP1,JP2,JP3,JP4,JP5,JP6 JUMPER
4 1 J1 CON AT62
5 1 J2 DB25
6 1 RP1 20K
7 1 R1 10K
8 1 S1 SW DIP-8
9 1 U1 74HCT688

_______________________________________________________________________________________________

Philips Semiconductors - Asia Product Innovation Centre

Visit http://www.flexiusb.com