Philips PDI1394P24 Technical data

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PDI1394P24

2-port 400 Mbps physical layer interface

Objective data
Supersedes data of 2000 Aug 02

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2001 Sep 06

Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

1.0 FEATURES

•Fully supports provisions of IEEE 1394–1995 Standard for high

performance serial bus and the P1394a–2000 Standard.

1

• Fully interoperable with Firewire and i.LINK implementations of

the IEEE 1394 Standard.

2

•Full P1394a support includes:

– Connection debounce
– Arbitrated short reset
– Multispeed concatenation
– Arbitration acceleration
– Fly-by concatenation
– Port disable/suspend/resume

•Provides two 1394a fully-compliant cable ports at

100/200/400 Megabits per second (Mbps)

•Fully compliant with Open HCI requirements

• Cable ports monitor line conditions for active connection to remote

node.

•Power down features to conserve energy in battery-powered

applications include:

– Automatic device power down during suspend
– Device power down terminal
– Link interface disable via LPS
– Inactive ports powered-down

•Logic performs system initialization and arbitration functions

•Encode and decode functions included for data-strobe bit level

encoding

•Incoming data resynchronized to local clock

•Single 3.3 volt supply operation

•Minimum V

of 2.7 V for end-of-wire power-consuming devices

DD

•While unpowered and connected to the bus, will not drive TPBIAS

on a connected port, even if receiving incoming bias voltage on
that port

•Supports extended bias-handshake time for enhanced

interoperability with camcorders

•Interface to link-layer controller supports both low-cost bus-holder

isolation and optional Annex J electrical isolation

•Data interface to link-layer controller through 2/4/8 parallel lines at

49.152 MHz

•Low-cost 24.576 MHz crystal provides transmit, receive data at

100/200/400 Mbps, and link-layer controller clock at 49.152 MHz

•Does not require external filter capacitors for PLL

•Interoperable with link-layer controllers using 3.3 V and 5 V

supplies

•Interoperable with other Physical Layers (PHYs) using 3.3 V and

5 V supplies

•Node power class information signaling for system power

management

•Cable power presence monitoring

•Separate cable bias (TPBIAS) for each port

•Register bits give software control of contender bit, power class

bits, link active bit, and 1394a features

•Function and pin compatible with the Lucent FW802 400 Mbps Phy

2.0 DESCRIPTION

The PDI1394P24 provides the digital and analog transceiver functions
needed to implement a two port node in a cable-based IEEE
1394–1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P24 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21.

3.0 ORDERING INFORMATION

PACKAGE TEMPERATURE RANGE ORDER CODE PKG. DWG. #

64-pin plastic LQFP 0 to +70°C PDI1394P24BD SOT314-2

1. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.

2. Firewire is a trademark of Apple Computer Inc. i.LINK is a trademark of Sony.

2001 Sep 06

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Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

4.0 PIN CONFIGURATION

LREQ

DGND

CTL0
CTL1

DVDD

DGND

CNA

LPS

DGND

SYSCLK

62 61 60 59 58 57 56 55 5464 63 53 52 51 50 49
1
2
3
4
5

D0

6

D1

7
8

D2

9

D3

10

D4

11

D5

12

D6

13

D7

14
15
16

19 20 21 22 23 24 25

DVDD

C/LKON

DVDD

PD

/RESET

PC0

XOXIPLLGND

PLLVDD

PDI1394P24

PC1

PC2

/ISO

CPS

DGND

26 2717 18

DGND

R1

R0

AGND

28 29 30 31 32

DVDD

DVDD

TEST1

AGND

TEST0

AVDD

AVDD

AVDD

AVDD

AGND

AGND

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

NC
NC
NC
NC
NC
AVDD
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
TPBIAS0
TPA0+
TPA0–
TPB0+
TPB0–

2001 Sep 06

SV001823

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Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

5.0 PIN DESCRIPTION

Name Pin Type Pin Numbers I/O Description

AGND Supply 32, 49, 52, 53 — Analog circuit ground terminals. These terminals should be tied together

AV

DD

C/LKON CMOS 5V tol 18 I/O Bus Manager Contender programming input and link-on output. On

CNA CMOS 15 O Cable Not Active output. This terminal is asserted high when there are

CPS CMOS 24 I Cable Power Status input. This terminal is normally connected to cable

CTL0,
CTL1

D0–D7 CMOS 5V tol 5, 6, 8, 9, 10, 1 1,

DGND Supply 2, 14, 25, 56, 64 — Digital circuit ground terminals. These terminals should be tied together

Supply 30, 31, 43, 50, 51 — Analog circuit power terminals. A combination of high frequency

CMOS 5V tol 3, 4 I/O Control I/Os. These bi-directional signals control communication

I/O Data I/Os. These are bi-directional data signals between the

12, 13

to the low impedance circuit board ground plane.

decoupling capacitors on each side are suggested, such as paralleled

0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also
recommended. These supply terminals are separated from PLLV

internal to the device to provide noise isolation. They should be

DV

DD

tied at a low impedance point on the circuit board.

hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10-kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.

If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-kΩ series resistor should be placed on this

line between the PHY and the LLC to prevent possible contention. In this

case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.

Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.

The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:

a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI

(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.

Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).

NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.

no ports receiving incoming bias voltage.

power through a 390 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.

between the PDI1394P24 and the LLC. Bus holders are built into
these terminals.

PDI1394P24 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 kΩ resistors.

to the low impedance circuit board ground plane.

DD

and

2001 Sep 06

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Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

Name DescriptionI/OPin NumbersPin Type

DV

DD

ISO CMOS 23 I Link interface isolation control input. This terminal controls the operation

LPS CMOS 5V tol 16 I Link Power Status input. This terminal is used to monitor the

LREQ CMOS 5V tol 1 I LLC Request input. The LLC uses this input to initiate a service request

NC No connect 44, 45, 46, 47, 48 — No connect.
PC0, PC1,

PC2

PD CMOS 5V tol 19 I Power Down input. A logic high on this terminal turns off all internal

PLLGND Supply 58 — PLL circuit ground terminals. These terminals should be tied together to

PLLV

DD

R0, R1 Bias 54, 55 — Current setting resistor terminals. These terminals are connected to

Supply 7, 17, 26, 27, 62 — Digital circuit power terminals. A combination of high frequency

CMOS 5V tol 20, 21, 22 I Power Class programming inputs. On hardware reset, these inputs set

Supply 57 — PLL circuit power terminals. A combination of high frequency decoupling

decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLV
isolation. They should be tied at a low impedance point on the circuit
board.

of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1995
is implemented between the PDI1394P24 and LLC, the ISO terminal

should be tied low to enable the differentiation logic. If no isolation barrier

is implemented (direct connection), or bus holder isolation is
implemented, the ISO
differentiation logic.

active/power status of the link layer controller and to control the state of
the PHY -LLC interface. This terminal should be connected to either the
VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output
which is active when the LLC is powered. A pulsed signal should be
used when an isolation barrier exists between the LLC and PHY. (See
Figure 8)

The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6 µs (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6 µs). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.

When the PDI1394P24 detects that LPS is inactive, it will place the
PHY -LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY -LLC interface is placed into the
disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.

to the PDI1394P24. Bus holder is built into this terminal.

the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.

circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2

the low impedance circuit board ground plane.

capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.

an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 2.49 kΩ ±1% is required to
meet the IEEE Std 1394–1995 output voltage limits.

and AVDD internal to the device to provide noise

DD

terminal should be tied high to disable the

2001 Sep 06

5

Philips Semiconductors Objective data

matched and as short as possible to the external load resistors and to

matched and as short as possible to the external load resistors and to

PDI1394P242-port 400 Mbps physical layer interface

Name DescriptionI/OPin NumbersPin Type

RESET CMOS 5V tol 61 I Logic reset input. Asserting this terminal low resets the internal logic. An

SYSCLK CMOS 63 O System clock output. Provides a 49.152 MHz clock signal, synchronized

TEST0 CMOS 29 I Test control input. This input is used in manufacturing tests of the

TEST1 CMOS 28 I Test control input. This input is used in manufacturing tests of the

TPA0+,
TPA1+

TPA0–,
TPA1–

TPB0+,
TPB1+

TPB0–,
TPB1–

TPBIAS0,
TPBIAS1

XO, XI Crystal 60, 59 — Crystal oscillator inputs. These terminals connect to a 24.576 MHz

Cable 36, 41 I/O

Cable 35, 40 I/O

Cable 34, 39 I/O

Cable 33, 38 I/O

Cable 37, 42 I/O Twisted-pair bias output. This provides the 1.86V nominal bias voltage

internal pull-up resistor to VDD is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.

with data transfers, to the LLC.

PDI1394P24. For normal use, this terminal should be tied to GND.

PDI1394P24. For normal use, this terminal should be tied to GND.
Twisted-pair cable A differential signal terminals. Board traces from each

pair of positive and negative differential signal terminals should be kept

p
the cable connector. TPA+ and TPA– can be left unconnected on an
unused port.

Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept

p
the cable connector. TPB+ and TPB– should be tied together and pulled
to ground on an unused port.

needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a

0.3 µF–1 µF capacitor to ground. TPBIAS can be left unconnected on an
unused port.

parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P24). For more information, refer to
Section 17.5.

2001 Sep 06

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Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

6.0 BLOCK DIAGRAM

LPS
/ISO

C/LKON

SYSCLK

LREQ

CTL0
CTL1

PC0
PC1
PC2

CNA

TPBIAS0
TPBIAS1

PD

/RESET

RECEIVED DATA

DECODER/

RETIMER

LINK
D0
D1
D2

D3
D4
D5
D6
D7

R0
R1

INTERFACE

I/O

ARBITRATION

AND CONTROL

STATE MACHINE

LOGIC

BIAS VOLTAGE

AND

CURRENT

GENERATOR

TRANSMIT

DATA

ENCODER

CABLE POWER

DETECTOR

CABLE PORT 0

CABLE PORT 1

CRYSTAL
OSCILLATOR,
PLL SYSTEM,

AND CLOCK

GENERATOR

CPS

TPA0+
TPA0–

TPB0+
TPB0–

TPA1+
TPA1–

TPB1+
TPB1–

XI
XO

SV01824

2001 Sep 06

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Philips Semiconductors Objective data

PDI1394P242-port 400 Mbps physical layer interface

7.0 FUNCTIONAL SPECIFICA TION

The PDI1394P24 requires only an external 24.576 MHz crystal as a
reference. An external clock can be connected to XI instead of a
crystal. An internal oscillator drives an internal phase-locked loop
(PLL), which generates the required 393.216 MHz reference signal.

This reference signal is internally divided to provide the clock signals

used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.

The PDI1394P24 supports an optional isolation barrier between
itself and its LLC. When the ISO
LLC interface outputs behave normally. When the ISO
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in

section 5.9.4

the ISO
using single capacitor isolation, please refer to the Philips Isolation
Application Note AN2452.

Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P24 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at

98.304/196.608/393.216 Mbps (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TP A cable
pair(s).

During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are

enabled. The encoded data information is received on the TPA cable

pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.

Both the TPA and TPB cable interfaces incorporate dif ferential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signaling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).

The PDI1394P24 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. The PHY contains two
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active

. To operate with single capacitor (bus holder) isolation,

on the PHY terminal must be tied high. For more details on

input terminal is tied high, the

terminal is

IEEE 1394a

connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.

The line drivers in the PDI1394P24 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable connections. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A terminals is connected

to its corresponding TPBIAS voltage terminal. The midpoint of the pair

of resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor has a value of 2.49 kΩ ±1%.

When the power supply of the PDI1394P24 is removed while the
twisted-pair cables are connected, the PDI1394P24 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.

When the PDI1394P24 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then

pulled to ground, or the TPB+ and TPB– terminals can be connected

to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.

The TEST0 and TEST1 terminals are used to set up various
manufacturing test conditions. For normal operation, the TEST0 and
TEST1 terminals should be connected to ground. TEST1 can also
be tied through a 1 kW resistor to ground.

Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 21 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.

The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all two ports of the PDI1394P24 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.

2001 Sep 06

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Philips Semiconductors Objective data

SYMBOL

PARAMETER

CONDITION

UNIT

Electrostatic discharge

PDI1394P242-port 400 Mbps physical layer interface

Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.

The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.

The CNA (cable-not-active) terminal provides a high when there are
no twisted-pair cable ports receiving incoming bias (i.e., they are
either disconnected or suspended), and can be used along with LPS
to determine when to power-down the PDI1394P24. The CNA
output is not debounced. When the PD terminal is asserted high, the
CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pull-down is activated on the RESET
as to force a reset of the PDI1394P24 internal logic.

The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY -LLC
interface (the state of the PHY -LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).

input terminal is asserted low), when no active

terminal so

The LPS input is considered inactive if it remains low for more than

2.6

µs and is considered active otherwise. When the PDI1394P24

detects that LPS is inactive, it will place the PHY -LLC interface into a
low-power reset state in which the CTL and D outputs are held in the

logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for

more than 26 µs, the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The
PHY -LLC interface is also held in the disabled state during hardware

reset. The PDI1394P24 will continue the necessary repeater

functions required for normal network operation regardless of the

state of the PHY -LLC interface. When the interface is in the reset or

disabled state and LPS is again observed active, the PHY will

initialize the interface and return it to normal operation.

The PHY uses the C/LKON terminal to notify the LLC to power up

and become active. When activated, the C/LKON signal is a square

wave of approximately 163 ns period. The PHY activates the

C/LKON output when the LLC is inactive and a wake-up event

occurs. The LLC is considered inactive when either the LPS input is

inactive, as described above, or the LCtrI bit is cleared to 0. A

wake-up event occurs when a link-on PHY packet addressed to this

node is received, or conditionally when a PHY interrupt occurs. The

PHY deasserts the C/LKON output when the LLC becomes active

(both LPS active and the LCtrl bit set to 1). The PHY also deasserts

the C/LKON output when a bus-reset occurs unless a PHY interrupt

condition exists which would otherwise cause C/LKON to be active.

8.0 ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).

V

VI–5V 5 volt tolerant input voltage range –0.5 5.5 V

V

T

amb

T

NOTE:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

DC supply voltage –0.5 4.0 V

DD

V

DC input voltage –0.5 VDD+0.5 V

I

DC output voltage range at any output –0.5 VDD+0.5 V

O

Operating free-air temperature range 0 +70 °C
Storage temperature range –65 +150 °C

stg

1

LIMITS

MIN MAX

Human Body Model — 2 kV

Machine Model — 200 V

2001 Sep 06

9

Philips Semiconductors Objective data

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VDDSu ly voltage

gg

VIDDifferential in ut voltage am litude

V

TPB common-mode in ut voltage

gg

V

TPB common-mode in ut voltage

S200 s eed signal

V

TPB common-mode in ut voltage

S400 s eed signal

PDI1394P242-port 400 Mbps physical layer interface

9.0 RECOMMENDED OPERATING CONDITIONS

pp

High-level input voltage, LREQ,
CTL0, CTL1, D0-D7

V

IH

High-level input voltage, C/LKON2,

Source power node 3.0 3.3 3.6 V
Non-source power node 2.7
ISO = VDD, VDD >= 2.7 V 2.3 — — V
ISO = VDD, VDD >= 3.0 V 2.6 — 5.5 V

PC0–PC2, ISO, PD
RESET 0.6 V
Low-level input voltage, LREQ,

CTL0, CTL1, D0–D7

V

Low-level input voltage, C/LKON2,

IL

PC0–PC2, ISO, PD,

ISO = V

DD

RESET — — 0.3 V

I

Output current TPBIAS outputs –6 — 2.5 mA

O

TPA, TPB cable inputs, during data reception 118 — 260 mV
TPA, TPB cable inputs, during data arbitration 168 — 265 mV

Speed signaling off
or S100 speed signal

p

p

Source power node 1.165 — 2.515 V
Non-source power node 1.165 — 2.015
Source power node 0.935 — 2.515 V
Non-source power node 0.935 — 2.015
Source power node 0.523 — 2.515 V
Non-source power node 0.523 — 2.015

IC-100

IC-200

IC-400

t

PU

p

p

p

p

p

Power–up reset time Set by capacitor between RESET pin and GND 2 — — ms

TPA, TPB cable inputs, S100 operation — — 1.08 ns

Receive input jitter

TPA, TPB cable inputs, S200 operation — — 0.5 ns
TPA, TPB cable inputs, S400 operation — — 0.315 ns

Between TPA and TPB cable inputs, S100 operation — — 0.8 ns

Receive input skew

Between TPA and TPB cable inputs, S200 operation — — 0.55 ns
Between TPA and TPB cable inputs, S400 operation — — 0.5 ns

f

XTAL

Crystal or external clock frequency

Crystal connected according to Figure 10 or external
clock input at pin XI

NOTES:

1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).

2. C/LKON is only an input when RESET

= 0.

1

3.0 3.6 V

0.7 V

— — V

DD

— —

DD

— — 0.7 V

— — 0.2 V

DD

DD

V

—

1

V

1

V

1

V

24.5735 24.576 24.5785 MHz

2001 Sep 06

10

Philips Semiconductors Objective data

SYMBOL

PARAMETER

TEST CONDITION

UNIT

I

gg , ,

SYMBOL

PARAMETER

TEST CONDITION

UNIT

ZIDDifferential input impedance

Drivers disabled

ZICCommon mode input impedance

Drivers disabled

PDI1394P242-port 400 Mbps physical layer interface

10.0 CABLE DRIVER

LIMITS

MIN TYP MAX

V

I

O(diff)

V

OFF

NOTES:

1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

2. Limits defined as one half of the algebraic sum of currents flowing out of TPB+ and TPB–.

11.0 CABLE RECEIVER

V

V

V

V

V

TH–SP200

V

TH–SP400

Differential output voltage 56 Ω load 172 — 265 mV

OD

Drivers enabled,

Driver Difference current, TP A+, TPA–, TPB+, TPB–

Common mode speed signaling output current, TPB+,
TPB–

2

SP

1

speed signaling OFF

–0.88 — 0.88 mA

200 Mbps speed signaling enabled –4.84 — –2.53 mA
400 Mbps speed signaling enabled –12.4 — –8.10 mA

OFF state differential voltage Drivers disabled — — 20 mV

LIMITS

MIN TYP MAX

10 14 —

— — 4 pF

20 — — kΩ

— — 24 pF

TH-R

TH-CB

TH+

TH–

p

p

p

p

Receiver input threshold voltage Drivers disabled –30 — 30 mV
Cable bias detect threshold, TPBn cable inputs Drivers disabled 0.6 — 1.0 V
Positive arbitration comparator input threshold

voltage
Negative arbitration comparator input threshold

voltage

Drivers disabled 89 — 168 mV

Drivers disabled –168 — –89 mV
TPBIAS–TPA common mode

Speed signal input threshold

voltage, drivers disabled 200

49 — 131 mV

Mbps
TPBIAS–TPA common mode

Speed signal input threshold

voltage, drivers disabled 400

314 — 396 mV

Mbps

I

CD

Connect detect output at TPBIAS pins Drivers disabled — — –76 µA

kΩ

2001 Sep 06

11

Philips Semiconductors Objective data

High level out ut voltage. ins CTL0

C/LKON

V

CTL1, D0–D7, CNA, C/LKON

PDI1394P242-port 400 Mbps physical layer interface

12.0 OTHER DEVICE I/O

SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT

See Note 1 — TBD — mA

I

DD

I

DD–PD

V

TH

V

OH

Supply current

Supply current in power down mode PD = VDD in power down mode — TBD — µA

Cable power status threshold voltage

-

p

p

CTL1, D0–D7, SYSCLK, CNA,

Low-level output voltage, pins CTL0,

OL

I

BH+

I

BH–

I

I

I

OZ

I

RST-UP

I

RST-DN

V

IT+

V

IT–

V

LIT+

V

LIT–

V

O

SYSCLK
Positive peak bus holder current, pins

CTL0, CTL1, D0–D7, LREQ
Negative peak bus holder current, pins

CTL0, CTL1, D0–D7, LREQ
Input current, pins LREQ, LPS, PD,

TEST0, TEST1, PC0–PC2
Off-state current, pins CTL0, CTL1,

D0–D7, C/LKON
Pullup current, RESET input VI = 1.5 V or 0 V –90 — –20 µA
Pulldown current, RESET input VI = VDD, PD = V
Positive going threshold voltage, LREQ,

CTL0, CTL1, D0–D7, C/LKON inputs
Negative going threshold voltage, LREQ,

CTL0, CTL1, D0–D7, C/LKON inputs
Positive going threshold voltage, LPS

inputs
Negative going threshold voltage, LPS

inputs
TPBIAS output voltage At rated IO current 1.665 — 2.015 V

,

NOTES:

1. Transmit Max Packet (2 ports transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value
of 0xCCCCCCCCh), V

2. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 1 port repeating the packet, S100), V

= 3.3 V, TA = 25°C

DD

TA = 25°C

3. Idle (receive cycle start on one port, transmit cycle start on other port) V

See Note 2 — TBD — mA
See Note 3 — TBD — mA

390 kΩ resistor between cable power
and CPS pin: Measured at cable power

4.7 — 7.5 V

side of resistor
VDD >= 2.7 V, IOH = –4 mA, ISO = V

,

VDD >= 3.0 V, IOH = –4 mA, ISO = V

DD
DD

2.4 — — V

2.8 — — V

Annex J: IOH = –9 mA, ISO = 0 VDD–0.4 — — V
IOL = 4 mA, ISO = V

DD

— — 0.4 V

Annex J: IOL = 9 mA, ISO = 0 — — 0.4 V
ISO = VDD, VI = 0 V to V

ISO = VDD, VI = 0 V to V

DD

DD

0.05 — 1.0 mA

–1.0 — –0.05 mA

ISO = 0 V; VDD = 3.6 V — — 5 µA

VO = VDD or 0 V –5 — 5 µA

DD

.4 1.6 2.8 mA

ISO = 0 V VDD/2 + 0.3 — VDD/2 + 0.9 V

ISO = 0 V VDD/2 – 0.9 — VDD/2 – 0.3 V

V

V

LREF

LREF

= 0.24 × V

= 0.24 × V

DD

DD

= 3.3 V, TA = 25°C

DD

— — V

V

+0.2 — — V

LREF

LREF

= 3.3 V,

DD

+1 V

2001 Sep 06

12