Philips PCK351 Technical data
1. Description
2. Features
PCK351
1:10 clock distribution device with 3-State outputs
Rev. 01 — 14 May 2002 Product data
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The
PCK351 enables a single clock input to be distributed to ten outputs with minimum
output skew andpulse skew.The use of distributed VCCand GND pins in the PCK351
ensures reduced switching noise.
The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and
over the industrial temperature range −40 to +85 °C.
■ 1:10 LVTTL clock distribution
■ Low output to output skew
■ Low output pulse skew
■ Over voltage tolerant inputs and outputs
■ LVTTL-compatible inputs and outputs
■ Distributed VCC and ground pins reduce switching noise
■ Balanced High-drive outputs (−32 mA IOH, 32 mA IOL)
■ Reduced power dissipation due to the state-of-the-art QUBiC-LP process
■ Supply range of +3.0 V to +3.6 V
■ Package options include plastic small-outline (D) and shrink small-outline (DB)
packages
■ Industrial temperature range −40 to +85 °C
■ PCK351 is identical to and replaces PTN3151.
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T
Symbol Parameter Conditions Min Typ Max Unit
t
PHL/tPLH
C
I
C
O
C
PD
=25°C; tr=t
amb
propagation delay: A to Y
≤
f
3.0 ns.
n
CL= 50 pF; VCC= 3.3 V 3.1 3.6 4.1 ns
input capacitance VI=VCCor GND - 4 - pF
output capacitance VI=VCCor GND - 6 - pF
power dissipation capacitance
[1]
CL= 50 pF; f = 1 MHz - 48 - pF
[1] CPDis used to determine the dynamic power dissipation (PDin µW).
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs;
CC
2
× fo) where:
CC
4. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
PCK351D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCK351DB SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
9397 75009791
Product data Rev. 01 — 14 May 2002 2 of 17
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Philips Semiconductors
5. Pinning information
5.1 Pinning
PCK351
1:10 clock distribution device with 3-State outputs
GND
Y
V
CC
Y
OE
GND
GND
Y
V
CC
Y
GND
1
2
10
3
4
9
5
6
A
7
8
9
8
10
11
7
12
PCK351D
002aaa280
GND
24
Y
23
1
V
22
CC
Y
21
2
GND
20
Y
19
3
Y
18
4
GND
17
Y
16
5
V
15
CC
Y
14
6
GND
13
GND
Y
V
CC
Y
OE
GND
GND
Y
V
CC
Y
GND
1
2
10
3
4
9
5
6
A
7
8
9
8
10
11
7
12
002aaa281
Fig 1. SO24 pin configuration. Fig 2. SSOP24 pin configuration.
5.2 Pin description
Table 3: Pin description
Symbol Pin Description
GND 1, 7, 8, 12, 13, 17, 20, 24 ground (0 V)
to Y
Y
10
V
CC
OE 5 output enable input (Active-LOW)
A 6 data input
2, 4, 9, 11, 14, 16, 18, 19, 21, 23 outputs
1
3, 10, 15, 22 supply voltage
24
23
22
21
20
19
18
PCK351DB
17
16
15
14
13
GND
Y
1
V
CC
Y
2
GND
Y
3
Y
4
GND
Y
5
V
CC
Y
6
GND
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 14 May 2002 3 of 17
Philips Semiconductors
6. Functional description
6.1 Function table
Table 4: Function table
A OE Y
LH Z
HH Z
LL L
HL H
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
6.2 Logic symbol
PCK351
1:10 clock distribution device with 3-State outputs
Inputs Outputs
n
Fig 3. Logic symbol.
OE
5
EN
23
Y
1
21
Y
2
19
Y
3
18
Y
4
16
6
A
002aaa283
Y
5
14
Y
6
11
Y
7
9
Y
8
4
Y
9
2
Y
10
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 14 May 2002 4 of 17
Philips Semiconductors
6.3 Logic diagram
PCK351
1:10 clock distribution device with 3-State outputs
5
OE
23
Y
1
21
Y
2
19
Y
3
18
Y
6
A
4
16
Y
5
14
Y
6
11
Y
7
Fig 4. Logic diagram.
9
4
2
002aaa282
Y
8
Y
9
Y
10
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 14 May 2002 5 of 17
Philips Semiconductors
7. Limiting values
PCK351
1:10 clock distribution device with 3-State outputs
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1],[2]
Symbol Parameter Conditions Min Max Unit
V
CC
V
I
V
O
I
IK
I
OK
I
O
, I
I
CC
GND
T
stg
P
D
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated
under ‘recommended operating conditions’ is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum
junction temperature of this integrated circuit should not exceed 150 °C.
[3] The input and output negative voltage ratings may be exceeded if the input and output clamp currents
are observed.
supply voltage range −0.5 +4.6 V
input voltage range
output voltage range
[3]
−0.5 +7.0 V
[3]
−0.5 +3.6 V
input clamp current VI<0V - −18 mA
output clamp current VI<0V - −50 mA
output sink current - 64 mA
VCC or GND current - ±75 mA
storage temperature −65 +150 °C
maximum power dissipation
SO package T
SSOP package T
= +55 °C - 0.65 W
amb
= +55 °C - 1.7 W
amb
8. Recommended operating conditions
Table 6: Recommended operating conditions
See note 1.
Symbol Parameter Conditions Min Max Unit
V
CC
V
IH
V
I
T
amb
, t
t
r
f
[1] Unused pins (input or I/O) must be held HIGH or LOW.
supply voltage 3.0 3.6 V
HIGH-level input voltage 2.0 5.5 V
input voltage 0 0.8 V
ambient temperature see Table 7 “DC
input rise and fall times VCC= 3.3 ±0.3 V - 100 ns/V
−40 +85 °C
characteristics”
and Table 8 “AC
characteristics”
per device
9397 750 09791
Product data Rev. 01 — 14 May 2002 6 of 17
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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