Philips P89C60X2, P89C61X2 Technical data
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INTEGRATED CIRCUITS
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash
512B/1024B RAM
Product data
Supersedes data of 2002 Jul 23
2003 Sep 11
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
DESCRIPTION
The Philips microcontrollers described in this data sheet are
high-performance static 80C51 designs. They are manufactured in
an advanced CMOS process and contain a non-volatile Flash
program memory that is programmable in parallel (via a parallel
programmer) or In-System Programmable (ISP) via boot loader.
They support both 12-clock and 6-clock operation.
The P89C60X2 and P89C61X2 contain 512 bytes RAM and
1024 bytes RAM respectively, 32 I/O lines, three 16-bit
counter/timers, a six-source, four-priority level nested interrupt
structure, a serial I/O port for either multi-processor
communications, I/O expansion or full duplex UART, and on-chip
oscillator and clock circuits.
Type Memory Timers Serial Interfaces
RAM
ROM
OTP
P89C60X2
P89C61X2
NOTE:
2
C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;
1. I
512B – – 64K 3 – –
1024B – – 64K 3 – –
Flash
# of Timers
PWM
PCA
WD
n n
n n
2
UART
– – – – 32 6 (2)
– – – – 32 6 (2)
In addition, the devices are static designs which offer a wide range
of operating frequencies down to zero. Two software selectable
modes of power reduction — idle mode and power-down mode —
are available. The idle mode freezes the CPU while allowing the
RAM, timers, serial port, and interrupt system to continue
functioning. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative. Since the design is static, the clock can be stopped
without loss of user data. Then the execution can be resumed from
the point the clock was stopped.
SELECTION TABLE
For applications requiring more RAM, as well as more on-chip
peripherals, see the P89C66x and P89C51Rx2 data sheets.
C
I
CAN
SPI
ADC bits/ch.
I/O Pins
Interrupts
(External)
Program
Security
n
n
P89C60X2/61X2
Max.
Freq.
Freq.
Range
at 6-clk
at 3V
/ 12-clk
(MHz)
Optional
Clock Rate
(MHz)
Default Clock
Rate
12–clk 6-clk 20/33 – 0–20/33
12–clk 6-clk 20/33 – 0–20/33
ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation
Freq.
Range
at 5V
(MHz)
2003 Sep 1 1 853-2400 30250
2
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
FEATURES
•80C51 Central Processing Unit
– 64 kbytes Flash
– 512 bytes RAM (P89C60X2)
– 1024 bytes RAM (P89C61X2)
– Boolean processor
– Fully static operation
•In-System Programmable (ISP) Flash memory
•12-clock operation with selectable 6-clock operation (via software
or via parallel programmer)
•Memory addressing capability
– Up to 64 kbytes ROM and 64 kbytes RAM
•Power control modes:
– Clock can be stopped and resumed
– Idle mode
– Power-down mode
•Two speed ranges
– 0 to 20 MHz with 6-clock operation
– 0 to 33 MHz with 12-clock operation
P89C60X2/61X2
•LQFP, PLCC, and DIP packages
•Dual Data Pointers
•Three security bits
•Four interrupt priority levels
•Six interrupt sources
•Four 8-bit I/O ports
•Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
•Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
•Programmable clock-out pin
•Watchdog timer
•Asynchronous port reset
•Low EMI (inhibit ALE, 6-clock mode)
•Wake-up from Power Down by an external interrupt
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
P89C60X2/61X2
P89C60X2 ORDERING INFORMATION
Type number Package Temperature
Name Description Version
P89C60X2BA/00 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 0 to +70
P89C60X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70
P89C60X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70
Range (°C)
P89C61X2 ORDERING INFORMATION
Type number Package Temperature
Name Description Version
P89C61X2BA/00
P89C61X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70
P89C61X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70
PLCC44
plastic lead chip carrier; 44 leads
SOT187-2
Range (°C)
0 to +70
P ART NUMBER DERIVATION
Memory Temperature Range Package
P89C60X2
9 = Flash 0 = 512 bytes RAM
64 kbytes FLASH
1= 1024 bytes RAM
64 kbytes FLASH
X2 =6-clock
mode available
B = 0 °C to +70 °C A = PLCC
BD = LQFP
The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:
Operating Mode Power Supply Maximum Clock Frequency
6-clock 5 V ± 10% 20 MHz
12-clock 5 V ± 10% 33 MHz
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
BLOCK DIAGRAM 1
64 KBYTE
CODE FLASH
512 / 1024 BYTE
DATA RAM
PORT 3
CONFIGURABLE I/Os
P89C60X2/61X2
ACCELERATED 80C51 CPU
(12-CLK MODE, 6-CLK MODE)
FULL-DUPLEX
ENHANCED UART
TIMER 0
TIMER 1
TIMER 2
RESONATOR
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
OSCILLATORCRYSTAL OR
WATCHDOG
TIMER
su01664
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
BLOCK DIAGRAM 2 (CPU-ORIENTED)
V
CC
V
SS
RAM ADDR
REGISTER
B
REGISTER
RAM
ACC
TMP2
P0.0–P0.7 P2.0–P2.7
PORT 0
DRIVERS
PORT 0
LATCH
TMP1
PORT 2
DRIVERS
PORT 2
LATCH
STACK
POINTER
P89C60X2/61X2
FLASH
8
PROGRAM
ADDRESS
REGISTER
PSEN
ALE/PROG
EA / V
PP
RST
TIMING
AND
CONTROL
OSCILLATOR
XTAL1 XTAL2
INSTRUCTION
PD
REGISTER
PSW
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
ALU
SFRs
TIMERS
PORT 3
LATCH
PORT 3
DRIVERS
P3.0–P3.7
BUFFER
PC
INCRE-
MENTER
8 16
PROGRAM
COUNTER
DPTR’S
MULTIPLE
SU01671
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
LOGIC SYMBOL
V
V
SS
CC
XTAL1
ADDRESS AND
PORT 0
XTAL2
RST
EA/V
PP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
PORT 3
T1
WR
RD
SECONDARY FUNCTIONS
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6140
DATA BUS
T2
T2EX
PORT 1PORT 2
ADDRESS BUS
SU01672
P89C60X2/61X2
LOW PROFILE QUAD FLAT PACK
PIN FUNCTIONS
44 34
1
LQFP
11
12 22
Pin Function
1 P1.5
2 P1.6
3 P1.7
4 RST
5 P3.0/RxD
6 NIC*
7 P3.1/TxD
8 P3.2/INT0
9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
* NO INTERNAL CONNECTION
Pin Function
16 V
SS
17 NIC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12
23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE
28 NIC*
29 EA
/V
30 P0.7/AD7
PP
33
23
Pin Function
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 V
CC
39 NIC*
40 P1.0/T2
41 P1.1/T2EX
42 P1.2
43 P1.3
44 P1.4
SU01487
7
17
Pin Function
1 NIC*
2 P1.0/T2
3 P1.1/T2EX
4 P1.2
5 P1.3
6 P1.4
7 P1.5
8 P1.6
9 P1.7
10 RST
11 P3.0/RxD
12 NIC*
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
* NO INTERNAL CONNECTION
PLCC
18 28
Pin Function
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 V
SS
23 NIC*
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
39
29
Pin Function
31 P2.7/A15
32 PSEN
33 ALE
34 NIC*
35 EA/V
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 V
PP
CC
SU01062
PLASTIC DUAL IN-LINE PACKAGE PIN
FUNCTIONS
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
/P3.2
INT0
/P3.3
INT1
T0/P3.4
T1/P3.5
WR
/P3.6
/P3.7
RD
XTAL2
XTAL1
V
1
2
3
4
5
6
7
8
9
DUAL
10
IN-LINE
PACKAGE
11
12
13
14
15
16
17
18
19
20
SS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/V
PP
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
SU01780
2003 Sep 1 1
7
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
P89C60X2/61X2
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC PLCC DIP LQFP TYPE NAME AND FUNCTION
V
SS
V
CC
P0.0-0.7 43–36 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
P1.0–P1.7 2–9 1–8 40–44,
P2.0–P2.7 24–31 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
P3.0–P3.7 11,
RST 10 9 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
ALE/PROG 33 30 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
PSEN 32 29 26 O Program Store Enable: The read strobe to external program memory. When the device
EA/V
PP
22 20 16 I Ground: 0 V reference.
44 40 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down
1–3
2 1 40 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable
3 2 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control
13–19
10–17 5,
7–13
11 10 5 I RxD (P3.0): Serial input port
13 11 7 O TxD (P3.1): Serial output port
14 12 8 I INT0 (P3.2): External interrupt
15 13 9 I INT1 (P3.3): External interrupt
16 14 10 I T0 (P3.4): Timer 0 external input
17 15 11 I T1 (P3.5): Timer 1 external input
18 16 12 O WR (P3.6): External data memory write strobe
19 17 13 O RD (P3.7): External data memory read strobe
35 31 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the
operation.
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs
the code bytes during program verification and received code bytes during Flash
programming. External pull-ups are required during program verification.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the
low-order address byte during program memory verification. Alternate functions for Port 1
include:
Clock-Out)
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-u ps when emitting 1s. During accesses to external data memory
that use 8 -bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register. Some Port 2 pins receive the high order address bits during Flash programming
and verification.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features
of the 80C51 family, as listed below:
device. An internal diffused resistor to VSS permits a power-on reset using only an
external capacitor to VCC.
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (12-clk) or 1/3 (6-clk Mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will
be active only during a MOVX instruction.
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory. This pin also receives the 5 V / 12 V programming supply voltage
(VPP) during Flash programming. If security bit 1 is programmed, EA will be internally latched on Reset.
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
PIN NUMBER
MNEMONIC NAME AND FUNCTIONTYPELQFPDIPPLCC
XTAL1 21 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
XTAL2 20 18 14 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
generator circuits.
+ 0.5 V or VSS – 0.5 V, respectively.
CC
P89C60X2/61X2
2003 Sep 1 1
9
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
P89C60X2/61X2
SPECIAL FUNCTION REGISTERS (see notes on next page)
SYMBOL DESCRIPTION
ACC* Accumulator E0H
AUXR# Auxiliary 8EH – – – – – –
AUXR1# Auxiliary 1 A2H – – – – GF2 0 – DPS xxx000x0B
B* B register F0H
CKCON Clock Control Register 8FH – WDX2 – – – – – X2 x0xxxxx0B
DPTR: Data Pointer (2 bytes)
DPH Data Pointer High 83H 00H
DPL Data Pointer Low 82H 00H
IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B
IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B
IPH# Interrupt Priority High B7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B
P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH
P1* Port 1 90H – – – – – – T2EX T2 FFH
P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB
E7 E6 E5 E4 E3 E2 E1 E0
F7 F6 F5 F4 F3 F2 F1 F0
AF AE AD AC AB AA A9 A8
BF BE BD BC BB BA B9 B8
87 86 85 84 83 82 81 80
97 96 95 94 93 92 91 90
A7 A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
EXTRAM
AO xxxxxx00B
RESET
VALUE
00H
00H
PCON#1Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B
RACAP2H# Timer 2 Capture High CBH 00H
RACAP2L# Timer 2 Capture Low CAH 00H
SADDR# Slave Address A9H 00H
SADEN# Slave Address Mask B9H 00H
SBUF Serial Data Buffer 99H xxxxxxxxB
9F 9E 9D 9C 9B 9A 99 98
SCON* Serial Control 98H
SP Stack Pointer 81H 07H
TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H
T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B
TH0 Timer High 0 8CH 00H
TH1 Timer High 1 8DH 00H
TH2# Timer High 2 CDH 00H
TL0 Timer Low 0 8AH 00H
TL1 Timer Low 1 8BH 00H
TL2# Timer Low 2 CCH 00H
TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H
WDTRST Watchdog Timer Reset A6H
SM0/FE
8F 8E 8D 8C 8B 8A 89 88
CF CE CD CC CB CA C9 C8
SM1 SM2 REN TB8 RB8 TI RI 00H
2003 Sep 1 1
10
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
NOTES:
Special Function Registers (SFRs) accesses are restricted in the following ways:
1. Do not attempt to access any SFR locations not defined.
2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
3. SFR bits labeled ‘–’, ‘0’ or ‘1’ can ONLY be written and read as follows:
‘–’ MUST be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
‘0’ MUST be written with ‘0’, and will return a ‘0’ when read.
‘1’ MUST be written with ‘1’, and will return a ‘1’ when read.
*: SFRs are bit addressable.
#: SFRs are modified from or added to the 80C51 SFRs.
–: Reserved bits (see note above).
1
: Reset value depends on reset source.
P89C60X2/61X2
2003 Sep 1 1
11
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
FLASH EPROM MEMORY
GENERAL DESCRIPTION
The P89C60X2/61X2 Flash memory augments EPROM functionality
with in-circuit electrical erasure and programming. The Flash can be
read and written as bytes. The Chip Erase operation will erase the
entire program memory. The Block Erase function can erase any
Flash block. In-system programming (ISP) and standard parallel
programming are both available. On-chip erase and write timing
generation contribute to a user friendly programming interface.
The P89C60X2/61X2 Flash reliably stores memory contents even
after 10,000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. In addition, the
combination of advanced tunnel oxide processing and low internal
electric fields for erase and programming operations produces
reliable cycling. The P89C60X2/61X2 uses a +5 V V
perform the Program/Erase algorithms (12 V tolerant).
supply to
PP
FEA TURES
•Flash EPROM internal program memory with Block Erase.
•Internal 1-kbyte fixed BootROM, containing low-level in-system
programming routines and a default serial loader.
•Loader in BootROM allows in-system programming via the serial
port.
•Up to 64 kbytes external program memory if the internal program
memory is disabled (EA
= 0).
•Programming and erase voltage +5 V (+12 V tolerant).
•Read/Programming/Erase using ISP:
– Byte Programming (8 ms).
– Typical erase times:
Block Erase (4 kbytes) in 3 seconds.
Full-chip erase in 15 seconds.
•Parallel programming with 87C51 compatible hardware interface
to programmer.
P89C60X2/61X2
•Programmable security for the code in the Flash.
•10,000 minimum erase/program cycles for each byte.
•10-year minimum data retention.
FLASH PROGRAMMING AND ERASURE
There are two methods of erasing or programming of the Flash
memory that may be used. First, the on-chip ISP boot loader may be
invoked. Second, the Flash may be programmed or erased using
parallel method by using a commercially available EPROM
programmer. The parallel programming method used by these
devices is similar to that used by EPROM 87C51, but it is not
identical, and the commercially available programmer will need to
have support for these devices.
FLASH MEMORY CHARACTERISTICS
Flash User Code Memory Organization
The P89C60X2/61X2 contains 64 kbytes Flash user code program
memory organized into 4-kbyte blocks (see Figure 1).
Boot ROM
When the microcontroller programs its Flash memory during ISP, all
of the low level details are handled by code that is contained in a
1 kbyte BootROM. BootROM operations include: erase block,
program byte, verify byte, program security bit, etc.
Clock Mode
The clock mode feature sets operating frequency to be 1/12 or 1/6 of
the oscillator frequency . The clock mode configuration bit, FX2, is
located in the Security Block (See Table 1). FX2, when programmed,
will override the SFR clock mode bit (X2) in the CKCON register. If
FX2 is erased, then the SFR bit (X2) may be used to select between
6-clock and 12-clock mode.
2003 Sep 1 1
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
Table 1.
CLOCK MODE CONFIG BIT (FX2) X2 bit in CKCON DESCRIPTION
erased 0 12-clock mode (default)
erased 1 6-clock mode
programmed x 6-clock mode
NOTE:
1. Default clock mode after ChipErase is set to 12-clock.
P89C60X2
P89C61X2
FFFF
C000
PROGRAM
ADDRESS
8000
4000
2000
0000
Figure 1. Flash Memory Configuration
BLOCK 15
BLOCK 14
BLOCK 13
BLOCK 12
BLOCK 11
BLOCK 10
BLOCK 9
BLOCK 8
BLOCK 7
BLOCK 6
BLOCK 5
BLOCK 4
BLOCK 3
BLOCK 2
BLOCK 1
BLOCK 0
BOOT ROM
(1 kB)
Each block is
4 kbytes in size
P89C60X2/61X2
SU01673
Power-On Reset Code Execution
The P89C60X2/61X2 contains a special Flash register, the STATUS
BYTE. At the falling edge of reset, the P89C60X2/61X2 examines
the contents of the Status Byte. If the Status Byte is set to zero,
power-up execution starts at location 0000H, which is the normal
start address of the user’s application code. When the Status Byte is
set to a value other than zero, the factory masked-ROM ISP boot
loader is invoked. The factory default for the Status Byte is FFh.
Once set to 00h, the Status Byte can only be changed back to FFh
by a full-chip erase operation when using ISP.
2003 Sep 1 1
Hardware Activation of the Boot Loader
The boot loader can also be executed by holding PSEN LOW,
EA
greater than VIH (such as +5 V), and ALE HIGH (or not connected)
at the falling edge of RESET. This is the same effect as having a
non-zero status byte. This allows an application to be built that will
normally execute the end user’s code but can be manually forced
into ISP operation.
After programming the Flash, the status byte should be programmed
to zero in order to allow execution of the user’s application code
beginning at address 0000H.
13
Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
V
CC
RST
XTAL2
XTAL1
V
SS
Figure 2. In-System Programming with a Minimum of Pins
In-System Programming (ISP)
The In-System Programming (ISP) is performed without removing
the microcontroller from the system. The In-System Programming
(ISP) facility consists of a series of internal hardware resources
coupled with internal firmware to facilitate remote programming of
the P89C60X2/61X2 through the serial port. This firmware is
provided by Philips and embedded within each P89C60X2/61X2
device.
The Philips In-System Programming (ISP) facility has made in-circuit
programming in an embedded application possible with a minimum
of additional expense in components and circuit board area.
The ISP function uses five pins: TxD, RxD, V
Figure 2). Only a small connector needs to be available to interface
your application to an external circuit in order to use this feature.
The V
supply should be adequately decoupled and VPP not
PP
allowed to exceed datasheet limits.
Free ISP software is available from the Embedded Systems
Academy: “FlashMagic”
1. Direct your browser to the following page:
http://www.esacademy.com/software/flashmagic/
2. Download Flashmagic
3. Execute “flashmagic.exe” to install the software
Using the In-System Programming (ISP)
The ISP feature allows for a wide range of baud rates to be used in
your application, independent of the oscillator frequency. It is also
adaptable to a wide range of oscillator frequencies. This is
accomplished by measuring the bit-time of a single bit in a received
character. This information is then used to program the baud rate in
terms of timer counts based on the oscillator frequency. The ISP
feature requires that an initial character (an uppercase U) be sent to
the P89C60X2/61X2 to establish the baud rate. The ISP firmware
provides auto-echo of received characters.
Once baud rate initialization has been performed, the ISP firmware
will only accept Intel Hex-type records. Intel Hex records consist of
ASCII characters used to represent hexadecimal values and are
summarized below:
, VCC, and VPP (see
SS
P89C60X2
P89C61X2
P89C60X2/61X2
V
PP
V
CC
TxD
RxD
:NNAAAARRDD..DDCC<crlf>
In the Intel Hex record, the “NN” represents the number of data
bytes in the record. The P89C60X2/61X2 will accept up to 16 (10H)
data bytes. The “AAAA” string represents the address of the first
byte in the record. If there are zero bytes in the record, this field is
often set to 0000. The “RR” string indicates the record type. A
record type of “00” is a data record. A record type of “01” indicates
the end-of-file mark. In this application, additional record types will
be added to indicate either commands or data for the ISP facility.
The maximum number of data bytes in a record is limited to 16
(decimal). ISP commands are summarized in Table 2.
As a record is received by the P89C60X2/61X2, the information in
the record is stored internally and a checksum calculation is
performed. The operation indicated by the record type is not
performed until the entire record has been received. Should an error
occur in the checksum, the P89C60X2/61X2 will send an “X” out the
serial port indicating a checksum error. If the checksum calculation
is found to match the checksum in the record, then the command
will be executed. In most cases, successful reception of the record
will be indicated by transmitting a “.” character out the serial port
(displaying the contents of the internal program memory is an
exception).
In the case of a Data Record (record type 00), an additional check is
made. A “.” character will NOT be sent unless the record checksum
matched the calculated checksum and all of the bytes in the record
were successfully programmed. For a data record, an “X” indicates
that the checksum failed to match, and an “R” character indicates
that one of the bytes did not properly program. It is necessary to
send a type 02 record (specify oscillator frequency) to the
P89C60X2/61X2 before programming data.
The ISP facility was designed to that specific crystal frequencies
were not required in order to generate baud rates or time the
programming pulses. The user thus needs to provide the
P89C60X2/61X2 with information required to generate the proper
timing. Record type 02 is provided for this purpose.
+5 V (+12 V tolerant)
+5 V
TxD
RxD
V
SS
SU01674
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
Table 2. Intel-Hex Records Used by In-System Programming
RECORD TYPE COMMAND/DATA FUNCTION
00 Program Data
:nnaaaa00dd....ddcc
Where:
nn = number of bytes (hex) in record
aaaa = memory address of first byte in record
dd....dd = data bytes
cc = checksum
Example:
:10008000AF5F67F0602703E0322CFA92007780C3FD
01 End of File (EOF), no operation
:xxxxxx01cc
Where:
xxxxxx = required field, but value is a “don’t care”
cc = checksum
Example:
:00000001FF
03 Miscellaneous Write Functions
:nnxxxx03ffssddcc
Where:
nn = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
03 = Write Function
ff = subfunction code
ss = selection code
dd = data input (as needed)
cc = checksum
Subfunction Code = 04 (Set Status Byte to 00h)
ff = 04
ss = don’t care
Example:
:020000030400F7 set status byte to 00h (device executes user code after Reset)
Subfunction Code = 05 (Program Security Bits)
ff = 05
ss = 00 program security bit 1 (inhibit writing to Flash)
01 program security bit 2 (inhibit Flash verify)
02 program security bit 3 (disable external memory)
Example:
:020000030501F5 program security bit 2
Subfunction Code = 06 (Program Flash X2 bit)
ff = 06
ss = 02 program FX2 bit (dd = 80) ⇒ 6–clk. mode enabled
dd = data
Example 1:
:0300000306028072 program FX2 bit (enable 6–clk. mode)
P89C60X2/61X2
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
RECORD TYPE COMMAND/DATA FUNCTION
03 (cont.) Subfunction Code = 07 (Full Chip Erase)
Erases all blocks, security bits, and sets status byte to default values
ff = 07
ss = don’t care
dd = don’t care
Example:
:0100000307F5 full chip erase
Subfunction Code = 0C (Erase 4k blocks)
ff = 0C
ss = block code as shown below:
block 0, 0k ~ 4k, 00H
block 1, 4k ~ 8k, 10H
block 2, 8k ~ 12k, 20H
block 3, 12k ~ 16k, 30H
block 4, 16k ~ 20k, 40H
block 5, 20k ~ 24k, 50H
block 6, 24k ~ 28k, 60H
block 7, 28k ~ 32k, 70H
block 8, 32k ~ 36k, 80H
block 9, 36k ~ 40k, 90H
block 10, 40k ~ 44k, A0H
block 11, 44k ~ 48k, B0H
block 12, 48k ~ 52k, C0H
block 13, 52k ~ 56k, D0H
block 14, 56k ~ 60k, E0H
block 15, 60k ~ 64k, F0H
Example:
:020000030C20CF erase 4k block 2
04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out
the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that
address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is
initiated by the reception of any character and terminated by the reception of any character.
General Format of Function 04
:05xxxx04sssseeeeffcc
Where:
05 = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
04 = “Display Device Data or Blank Check” function code
ssss = starting address
eeee = ending address
ff = subfunction
00 = display data
01 = blank check
02 = display data in data block (valid addresses: 0001 ~ 0FFFH)
cc = checksum
Example 1:
:0500000440004FFF0069 display 4000–4FFF
Example 2:
:0500000400000FFF02E7 display data in data block (the data at address 0000 is
invalid)
P89C60X2/61X2
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Philips Semiconductors Product data
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
RECORD TYPE COMMAND/DATA FUNCTION
05 Miscellaneous Read Functions
General Format of Function 05
:02xxxx05ffsscc
Where:
02 = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
05 = “Miscellaneous Read” function code
ffss = subfunction and selection code
0000 = read signature byte – manufacturer id (15H)
0001 = read signature byte – device id # 1 (C2H)
0002 = read signature byte – device id # 2
P89C60X2 = EFh
P89C61X2 = F0h
0003 = read FX2 bit
0080 = read ROM code revision
0700 = read security bits
0701 = read status byte
cc = checksum
Example 1:
:020000050001F8 read signature byte – device id # 1
Example 2:
:020000050003F6 read FX2 bit (bit 7 = 0 represents 12-clk mode, bit 7 = 1
represents 6-clk mode)
Example 3:
:02000005008079 read ROM code revision (0A: Rev. A; 0B: Rev. B, etc.)
06 Direct Load of Baud Rate
General Format of Function 06
:02xxxx06hhllcc
Where:
02 = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
06 = ”Direct Load of Baud Rate” function code
hh = high byte of Timer 2
ll = low byte of Timer 2
cc = checksum
Example:
:02000006F500F3
P89C60X2/61X2
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Philips Semiconductors Product data
PROTECTION DESCRIPTION
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
P89C60X2/61X2
Security
The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are
located in FLASH. The P89C60X2/61X2 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code
and data (see Table 3). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1.
Table 3.
SECURITY LOCK BITS
Level
LB1
LB2 Program verification is disabled
LB3 External execution is disabled.
NOTE:
1. The security lock bits are independent.
1
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory.
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