Datasheet P89C60X2, P89C61X2 Datasheet (Philips)

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P89C60X2/61X2

80C51 8-bit Flash microcontroller family

64KB Flash 512B/1024B RAM

Product data Supersedes data of 2002 Jul 23

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2003 Sep 11

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

DESCRIPTION

The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs. They are manufactured in an advanced CMOS process and contain a non-volatile Flash program memory that is programmable in parallel (via a parallel programmer) or In-System Programmable (ISP) via boot loader. They support both 12-clock and 6-clock operation.

The P89C60X2 and P89C61X2 contain 512 bytes RAM and 1024 bytes RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.

Type Memory Timers Serial Interfaces

RAM

ROM

OTP

P89C60X2 P89C61X2

NOTE:

C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;

1. I

512B – – 64K 3 – –

1024B – – 64K 3 – –

Flash

# of Timers

PWM

PCA

n n

UART

– – – – 32 6 (2) – – – – 32 6 (2)

In addition, the devices are static designs which offer a wide range of operating frequencies down to zero. Two software selectable modes of power reduction — idle mode and power-down mode — are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped.

SELECTION TABLE

For applications requiring more RAM, as well as more on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets.

C I

CAN

SPI

ADC bits/ch.

I/O Pins

Interrupts

(External)

Program

Security

P89C60X2/61X2

Max.

Freq.

Range

at 6-clk

at 3V

/ 12-clk

(MHz)

Optional

Clock Rate

(MHz)

Default Clock

Rate

12–clk 6-clk 20/33 – 0–20/33 12–clk 6-clk 20/33 – 0–20/33

ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation

Freq. Range at 5V (MHz)

2003 Sep 1 1 853-2400 30250

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

FEATURES

•80C51 Central Processing Unit

– 64 kbytes Flash – 512 bytes RAM (P89C60X2) – 1024 bytes RAM (P89C61X2) – Boolean processor – Fully static operation

•In-System Programmable (ISP) Flash memory

•12-clock operation with selectable 6-clock operation (via software

or via parallel programmer)

•Memory addressing capability

– Up to 64 kbytes ROM and 64 kbytes RAM

•Power control modes:

– Clock can be stopped and resumed – Idle mode – Power-down mode

•Two speed ranges

– 0 to 20 MHz with 6-clock operation – 0 to 33 MHz with 12-clock operation

P89C60X2/61X2

•LQFP, PLCC, and DIP packages

•Dual Data Pointers

•Three security bits

•Four interrupt priority levels

•Six interrupt sources

•Four 8-bit I/O ports

•Full-duplex enhanced UART

– Framing error detection – Automatic address recognition

•Three 16-bit timers/counters T0, T1 (standard 80C51) and

additional T2 (capture and compare)

•Programmable clock-out pin

•Watchdog timer

•Asynchronous port reset

•Low EMI (inhibit ALE, 6-clock mode)

•Wake-up from Power Down by an external interrupt

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

P89C60X2 ORDERING INFORMATION

Type number Package Temperature

Name Description Version

P89C60X2BA/00 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 0 to +70 P89C60X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70 P89C60X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70

Range (°C)

P89C61X2 ORDERING INFORMATION

Type number Package Temperature

Name Description Version

P89C61X2BA/00 P89C61X2BN/00 DIP40 plastic dual in-line package; 40 leads SOT129-1 0 to +70 P89C61X2BBD/00 LQFP44 plastic low profile quad flat package; 44 leads SOT389-1 0 to +70

PLCC44

plastic lead chip carrier; 44 leads

SOT187-2

Range (°C)

0 to +70

P ART NUMBER DERIVATION

Memory Temperature Range Package

P89C60X2

9 = Flash 0 = 512 bytes RAM

64 kbytes FLASH

1= 1024 bytes RAM

64 kbytes FLASH

X2 =6-clock

mode available

B = 0 °C to +70 °C A = PLCC

BD = LQFP

The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:

Operating Mode Power Supply Maximum Clock Frequency

6-clock 5 V ± 10% 20 MHz 12-clock 5 V ± 10% 33 MHz

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

BLOCK DIAGRAM 1

64 KBYTE

CODE FLASH

512 / 1024 BYTE

DATA RAM

PORT 3

CONFIGURABLE I/Os

P89C60X2/61X2

ACCELERATED 80C51 CPU

(12-CLK MODE, 6-CLK MODE)

FULL-DUPLEX

ENHANCED UART

TIMER 0 TIMER 1

TIMER 2

RESONATOR

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

OSCILLATORCRYSTAL OR

WATCHDOG

TIMER

su01664

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

BLOCK DIAGRAM 2 (CPU-ORIENTED)

RAM ADDR REGISTER

RAM

ACC

TMP2

P0.0–P0.7 P2.0–P2.7

PORT 0

DRIVERS

PORT 0

LATCH

TMP1

PORT 2

DRIVERS

PORT 2

LATCH

STACK

POINTER

P89C60X2/61X2

FLASH

PROGRAM

ADDRESS

PSEN

ALE/PROG

EA / V

RST

TIMING

AND

CONTROL

OSCILLATOR

XTAL1 XTAL2

INSTRUCTION

PSW

PORT 1

LATCH

PORT 1

DRIVERS

P1.0–P1.7

ALU

SFRs

TIMERS

PORT 3

LATCH

PORT 3

DRIVERS

P3.0–P3.7

BUFFER

INCRE-

MENTER

8 16

PROGRAM COUNTER

DPTR’S

MULTIPLE

SU01671

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

LOGIC SYMBOL

XTAL1

ADDRESS AND

PORT 0

XTAL2

RST

EA/V

PSEN

ALE/PROG RxD TxD

INT0 INT1

PORT 3

SECONDARY FUNCTIONS

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

6140

DATA BUS

T2 T2EX

PORT 1PORT 2

ADDRESS BUS

SU01672

P89C60X2/61X2

LOW PROFILE QUAD FLAT PACK PIN FUNCTIONS

44 34

LQFP

12 22

Pin Function

1 P1.5 2 P1.6 3 P1.7 4 RST 5 P3.0/RxD 6 NIC* 7 P3.1/TxD 8 P3.2/INT0

9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD 14 XTAL2 15 XTAL1

* NO INTERNAL CONNECTION

Pin Function

16 V

17 NIC* 18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15 26 PSEN 27 ALE 28 NIC* 29 EA

30 P0.7/AD7

Pin Function

31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V

39 NIC* 40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4

SU01487

Pin Function

1 NIC* 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6

9 P1.7 10 RST 11 P3.0/RxD 12 NIC* 13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1

* NO INTERNAL CONNECTION

PLCC

18 28

Pin Function

16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD 20 XTAL2 21 XTAL1 22 V

23 NIC* 24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14

Pin Function

31 P2.7/A15 32 PSEN 33 ALE 34 NIC* 35 EA/V 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V

SU01062

PLASTIC DUAL IN-LINE PACKAGE PIN FUNCTIONS

T2/P1.0

T2EX/P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST RxD/P3.0 TxD/P3.1

/P3.2

INT0

/P3.3

INT1

T0/P3.4 T1/P3.5

/P3.6 /P3.7

XTAL2 XTAL1

1 2 3 4 5 6 7 8 9

DUAL

IN-LINE

PACKAGE

11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/V

ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8

SU01780

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC PLCC DIP LQFP TYPE NAME AND FUNCTION

P0.0-0.7 43–36 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

P1.0–P1.7 2–9 1–8 40–44,

P2.0–P2.7 24–31 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have

P3.0–P3.7 11,

RST 10 9 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE/PROG 33 30 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

PSEN 32 29 26 O Program Store Enable: The read strobe to external program memory. When the device

EA/V

22 20 16 I Ground: 0 V reference. 44 40 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down

1–3

2 1 40 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable 3 2 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control

13–19

10–17 5,

7–13

11 10 5 I RxD (P3.0): Serial input port 13 11 7 O TxD (P3.1): Serial output port 14 12 8 I INT0 (P3.2): External interrupt 15 13 9 I INT1 (P3.3): External interrupt 16 14 10 I T0 (P3.4): Timer 0 external input 17 15 11 I T1 (P3.5): Timer 1 external input 18 16 12 O WR (P3.6): External data memory write strobe 19 17 13 O RD (P3.7): External data memory read strobe

35 31 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the

operation. them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during Flash programming. External pull-ups are required during program verification.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the

internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for Port 1 include:

Clock-Out)

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-u ps when emitting 1s. During accesses to external data memory that use 8 -bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during Flash programming and verification.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below:

device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC.

address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (12-clk) or 1/3 (6-clk Mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory. This pin also receives the 5 V / 12 V programming supply voltage (VPP) during Flash programming. If security bit 1 is programmed, EA will be internally latched on Reset.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

PIN NUMBER

MNEMONIC NAME AND FUNCTIONTYPELQFPDIPPLCC

XTAL1 21 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock XTAL2 20 18 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

generator circuits.

+ 0.5 V or VSS – 0.5 V, respectively.

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

SPECIAL FUNCTION REGISTERS (see notes on next page)

SYMBOL DESCRIPTION

ACC* Accumulator E0H AUXR# Auxiliary 8EH – – – – – – AUXR1# Auxiliary 1 A2H – – – – GF2 0 – DPS xxx000x0B B* B register F0H CKCON Clock Control Register 8FH – WDX2 – – – – – X2 x0xxxxx0B DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H

IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B

IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B IPH# Interrupt Priority High B7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

P1* Port 1 90H – – – – – – T2EX T2 FFH

P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH

P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

MSB LSB

E7 E6 E5 E4 E3 E2 E1 E0

F7 F6 F5 F4 F3 F2 F1 F0

AF AE AD AC AB AA A9 A8

BF BE BD BC BB BA B9 B8

87 86 85 84 83 82 81 80

97 96 95 94 93 92 91 90

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

EXTRAM

AO xxxxxx00B

RESET VALUE

00H

PCON#1Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B

RACAP2H# Timer 2 Capture High CBH 00H RACAP2L# Timer 2 Capture Low CAH 00H

SADDR# Slave Address A9H 00H SADEN# Slave Address Mask B9H 00H SBUF Serial Data Buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98

SCON* Serial Control 98H SP Stack Pointer 81H 07H

TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H WDTRST Watchdog Timer Reset A6H

SM0/FE

8F 8E 8D 8C 8B 8A 89 88

CF CE CD CC CB CA C9 C8

SM1 SM2 REN TB8 RB8 TI RI 00H

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

NOTES:

Special Function Registers (SFRs) accesses are restricted in the following ways:

1. Do not attempt to access any SFR locations not defined.

2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

3. SFR bits labeled ‘–’, ‘0’ or ‘1’ can ONLY be written and read as follows: ‘–’ MUST be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. ‘0’ MUST be written with ‘0’, and will return a ‘0’ when read. ‘1’ MUST be written with ‘1’, and will return a ‘1’ when read.

*: SFRs are bit addressable. #: SFRs are modified from or added to the 80C51 SFRs. –: Reserved bits (see note above).

: Reset value depends on reset source.

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

FLASH EPROM MEMORY

GENERAL DESCRIPTION

The P89C60X2/61X2 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming (ISP) and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface.

The P89C60X2/61X2 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C60X2/61X2 uses a +5 V V perform the Program/Erase algorithms (12 V tolerant).

supply to

FEA TURES

•Flash EPROM internal program memory with Block Erase.

•Internal 1-kbyte fixed BootROM, containing low-level in-system

programming routines and a default serial loader.

•Loader in BootROM allows in-system programming via the serial

port.

•Up to 64 kbytes external program memory if the internal program

memory is disabled (EA

= 0).

•Programming and erase voltage +5 V (+12 V tolerant).

•Read/Programming/Erase using ISP:

– Byte Programming (8 ms). – Typical erase times:

Block Erase (4 kbytes) in 3 seconds. Full-chip erase in 15 seconds.

•Parallel programming with 87C51 compatible hardware interface

to programmer.

P89C60X2/61X2

•Programmable security for the code in the Flash.

•10,000 minimum erase/program cycles for each byte.

•10-year minimum data retention.

FLASH PROGRAMMING AND ERASURE

There are two methods of erasing or programming of the Flash memory that may be used. First, the on-chip ISP boot loader may be invoked. Second, the Flash may be programmed or erased using parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices.

FLASH MEMORY CHARACTERISTICS Flash User Code Memory Organization

The P89C60X2/61X2 contains 64 kbytes Flash user code program memory organized into 4-kbyte blocks (see Figure 1).

Boot ROM

When the microcontroller programs its Flash memory during ISP, all of the low level details are handled by code that is contained in a 1 kbyte BootROM. BootROM operations include: erase block, program byte, verify byte, program security bit, etc.

Clock Mode

The clock mode feature sets operating frequency to be 1/12 or 1/6 of the oscillator frequency . The clock mode configuration bit, FX2, is located in the Security Block (See Table 1). FX2, when programmed, will override the SFR clock mode bit (X2) in the CKCON register. If FX2 is erased, then the SFR bit (X2) may be used to select between 6-clock and 12-clock mode.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Table 1.

CLOCK MODE CONFIG BIT (FX2) X2 bit in CKCON DESCRIPTION

erased 0 12-clock mode (default) erased 1 6-clock mode programmed x 6-clock mode

NOTE:

1. Default clock mode after ChipErase is set to 12-clock.

P89C60X2 P89C61X2

FFFF

C000

PROGRAM

ADDRESS

8000

4000

2000

0000

Figure 1. Flash Memory Configuration

BLOCK 15

BLOCK 14

BLOCK 13

BLOCK 12

BLOCK 11

BLOCK 10

BLOCK 9

BLOCK 8

BLOCK 7

BLOCK 6

BLOCK 5

BLOCK 4

BLOCK 3

BLOCK 2

BLOCK 1

BLOCK 0

BOOT ROM

(1 kB)

Each block is 4 kbytes in size

P89C60X2/61X2

SU01673

Power-On Reset Code Execution

The P89C60X2/61X2 contains a special Flash register, the STATUS BYTE. At the falling edge of reset, the P89C60X2/61X2 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Status Byte is set to a value other than zero, the factory masked-ROM ISP boot loader is invoked. The factory default for the Status Byte is FFh. Once set to 00h, the Status Byte can only be changed back to FFh by a full-chip erase operation when using ISP.

2003 Sep 1 1

Hardware Activation of the Boot Loader

The boot loader can also be executed by holding PSEN LOW, EA

greater than VIH (such as +5 V), and ALE HIGH (or not connected) at the falling edge of RESET. This is the same effect as having a non-zero status byte. This allows an application to be built that will normally execute the end user’s code but can be manually forced into ISP operation.

After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H.

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

RST

XTAL2

XTAL1

Figure 2. In-System Programming with a Minimum of Pins

In-System Programming (ISP)

The In-System Programming (ISP) is performed without removing the microcontroller from the system. The In-System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89C60X2/61X2 through the serial port. This firmware is provided by Philips and embedded within each P89C60X2/61X2 device.

The Philips In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

The ISP function uses five pins: TxD, RxD, V Figure 2). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. The V

supply should be adequately decoupled and VPP not

allowed to exceed datasheet limits. Free ISP software is available from the Embedded Systems

Academy: “FlashMagic”

1. Direct your browser to the following page:

http://www.esacademy.com/software/flashmagic/

2. Download Flashmagic

3. Execute “flashmagic.exe” to install the software

Using the In-System Programming (ISP)

The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89C60X2/61X2 to establish the baud rate. The ISP firmware provides auto-echo of received characters.

Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:

, VCC, and VPP (see

P89C60X2 P89C61X2

P89C60X2/61X2

TxD RxD

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the “NN” represents the number of data bytes in the record. The P89C60X2/61X2 will accept up to 16 (10H) data bytes. The “AAAA” string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000. The “RR” string indicates the record type. A record type of “00” is a data record. A record type of “01” indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 16 (decimal). ISP commands are summarized in Table 2.

As a record is received by the P89C60X2/61X2, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89C60X2/61X2 will send an “X” out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a “.” character out the serial port (displaying the contents of the internal program memory is an exception).

In the case of a Data Record (record type 00), an additional check is made. A “.” character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record, an “X” indicates that the checksum failed to match, and an “R” character indicates that one of the bytes did not properly program. It is necessary to send a type 02 record (specify oscillator frequency) to the P89C60X2/61X2 before programming data.

The ISP facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. The user thus needs to provide the P89C60X2/61X2 with information required to generate the proper timing. Record type 02 is provided for this purpose.

+5 V (+12 V tolerant)

+5 V TxD RxD V

SU01674

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Table 2. Intel-Hex Records Used by In-System Programming

RECORD TYPE COMMAND/DATA FUNCTION

00 Program Data

:nnaaaa00dd....ddcc

Where:

nn = number of bytes (hex) in record aaaa = memory address of first byte in record

dd....dd = data bytes

cc = checksum

Example:

:10008000AF5F67F0602703E0322CFA92007780C3FD

01 End of File (EOF), no operation

:xxxxxx01cc

Where:

xxxxxx = required field, but value is a “don’t care” cc = checksum

Example:

:00000001FF

03 Miscellaneous Write Functions

:nnxxxx03ffssddcc

Where:

nn = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 03 = Write Function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum

Subfunction Code = 04 (Set Status Byte to 00h)

ff = 04 ss = don’t care

Example:

:020000030400F7 set status byte to 00h (device executes user code after Reset)

Subfunction Code = 05 (Program Security Bits)

ff = 05 ss = 00 program security bit 1 (inhibit writing to Flash) 01 program security bit 2 (inhibit Flash verify) 02 program security bit 3 (disable external memory)

Example:

:020000030501F5 program security bit 2

Subfunction Code = 06 (Program Flash X2 bit)

ff = 06 ss = 02 program FX2 bit (dd = 80) ⇒ 6–clk. mode enabled dd = data

Example 1:

:0300000306028072 program FX2 bit (enable 6–clk. mode)

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

RECORD TYPE COMMAND/DATA FUNCTION

03 (cont.) Subfunction Code = 07 (Full Chip Erase)

Erases all blocks, security bits, and sets status byte to default values

ff = 07 ss = don’t care dd = don’t care

Example:

:0100000307F5 full chip erase

Subfunction Code = 0C (Erase 4k blocks)

ff = 0C ss = block code as shown below:

block 0, 0k ~ 4k, 00H block 1, 4k ~ 8k, 10H block 2, 8k ~ 12k, 20H block 3, 12k ~ 16k, 30H block 4, 16k ~ 20k, 40H block 5, 20k ~ 24k, 50H block 6, 24k ~ 28k, 60H block 7, 28k ~ 32k, 70H block 8, 32k ~ 36k, 80H block 9, 36k ~ 40k, 90H block 10, 40k ~ 44k, A0H block 11, 44k ~ 48k, B0H block 12, 48k ~ 52k, C0H block 13, 52k ~ 56k, D0H block 14, 56k ~ 60k, E0H block 15, 60k ~ 64k, F0H

Example:

:020000030C20CF erase 4k block 2

04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out

the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is initiated by the reception of any character and terminated by the reception of any character.

General Format of Function 04

:05xxxx04sssseeeeffcc

Where:

05 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 04 = “Display Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction

00 = display data 01 = blank check 02 = display data in data block (valid addresses: 0001 ~ 0FFFH)

cc = checksum

Example 1:

:0500000440004FFF0069 display 4000–4FFF

Example 2:

:0500000400000FFF02E7 display data in data block (the data at address 0000 is

invalid)

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

RECORD TYPE COMMAND/DATA FUNCTION

05 Miscellaneous Read Functions

General Format of Function 05

:02xxxx05ffsscc

Where:

02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05 = “Miscellaneous Read” function code ffss = subfunction and selection code

0000 = read signature byte – manufacturer id (15H) 0001 = read signature byte – device id # 1 (C2H) 0002 = read signature byte – device id # 2

P89C60X2 = EFh

P89C61X2 = F0h 0003 = read FX2 bit 0080 = read ROM code revision 0700 = read security bits 0701 = read status byte

cc = checksum

Example 1:

:020000050001F8 read signature byte – device id # 1

Example 2:

:020000050003F6 read FX2 bit (bit 7 = 0 represents 12-clk mode, bit 7 = 1

represents 6-clk mode)

Example 3:

:02000005008079 read ROM code revision (0A: Rev. A; 0B: Rev. B, etc.)

06 Direct Load of Baud Rate

General Format of Function 06

:02xxxx06hhllcc

Where:

02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 06 = ”Direct Load of Baud Rate” function code hh = high byte of Timer 2 ll = low byte of Timer 2 cc = checksum

Example:

:02000006F500F3

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

PROTECTION DESCRIPTION

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

Security

The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The P89C60X2/61X2 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 3). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1.

Table 3.

SECURITY LOCK BITS

Level

LB1 LB2 Program verification is disabled

LB3 External execution is disabled.

NOTE:

1. The security lock bits are independent.

MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

OSCILLA T OR CHARACTERISTICS

Using the oscillator, XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. However, minimum and maximum high and low times specified in the data sheet must be observed.

Clock Control Register (CKCON)

This device provides control of the 6-clock/12-clock mode by both an SFR bit (bit X2 in register CKCON) and a Flash bit (bit FX2, located in the Security Block). When X2 is 0, 12-clock mode is activated. By setting this bit to 1, the system is switching to 6-clock mode. Having this option implemented as SFR bit, it can be accessed anytime and changed to either value. Changing X2 from 0 to 1 will result in executing user code at twice the speed, since all system time intervals will be divided by 2. Changing back from 6-clock to 12-clock mode will slow down running code by a factor of

2. The Flash clock control bit (FX2) activates the 6-clock mode when programmed using a parallel programmer, superceding the X2 bit (CKCON.0). Please also see Table 4 below.

Table 4.

FX2 clock mode bit (can only be set by parallel programmer)

erased 0 12-clock mode

erased 1 6-clock mode programmed X 6-clock mode

X2 bit (CKCON.0)

CPU clock mode

(default)

P89C60X2/61X2

Programmable Clock-Out Pin

A 50% duty cycle clock can be programmed to be output on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in 6-clock mode).

To configure the Timer/Counter 2 as a clock generator, bit C/T T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:

Oscillator Frequency

n (65536–RCAP2H,RCAP2L)

Where:

n = 2 in 6-clock mode, 4 in 12-clock mode. (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L

taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

RESET

A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods in 12-clock and 12 oscillator periods in 6-clock mode), while the oscillator is running. To insure a reliable power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles, unless it has been set to 6-clock operation using a parallel programmer.

2 (in

2003 Sep 1 1

LOW POWER MODES Stop Clock Mode

The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.

Idle Mode

In idle mode (see Table 5), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Power-Down Mode

To save even more power, a Power Down mode (see Table 5) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return V the minimum specified operating voltages before the Power Down Mode is terminated.

Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values.

To properly terminate Power Down, the reset or external interrupt should not be executed before V operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).

To terminate Power Down with an external interrupt, INT0 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.

is restored to its normal

Design Consideration

When the idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two

or INT1

P89C60X2/61X2

machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

ONCE Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked in the following way:

1. Pull ALE low while the device is in reset and PSEN

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

POWER-ON FLAG

The Power-On Flag (POF) is set by on-chip circuitry when the V level on the P89C60X2/61X2 rises from 0 to 5 V . The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The V unaffected by the V

level must remain above 3 V for the POF to remain

level.

is high;

are weakly pulled

Table 5. External Pin Status During Idle and Power-Down Modes

MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data

TIMER 0 AND TIMER 1 OPERATION Timer 0 and Timer 1

The “Timer” or “Counter” function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 T imer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 4 shows the Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register . As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The counted input is enabled to the Timer when TRn = 1 and either GA TE = 0 or INTn Timer to be controlled by external input INTn measurements). TRn is a control bit in the Special Function Register TCON (Figure 5).

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

= 1. (Setting GATE = 1 allows the

, to facilitate pulse width

Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GA TE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 6. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which is preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 as for Timer 1.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 7. TL0 uses the Timer 0 control bits: C/T pin INT0 cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt.

. TH0 is locked into a timer function (counting machine

, GATE, TR0, and TF0 as well as

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be

turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.

P89C60X2/61X2

TMOD Address = 89H Reset Value = 00H

Not Bit Addressable

76543 2 1 0

GATE C/T M1

M0 GATE C/T

M1 M0

TIMER 1 TIMER 0

BIT SYMBOL FUNCTION

TMOD.3/ GATE Gating control when set. Timer/Counter “n” is enabled only while “INTn” pin is high and TMOD.7 “TRn” control pin is set. when cleared Timer “n” is enabled whenever “TRn” control bit is set.

TMOD.2/ C/T

Timer or Counter Selector cleared for Timer operation (input from internal system clock.)

TMOD.6 Set for Counter operation (input from “Tn” input pin).

M1 M0 OPERATING

0 0 8048 Timer: “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter: “THn” and “TLn” are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter: “THn” holds a value which is to be reloaded

into “TLn” each time it overflows.

1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

1 1 (Timer 1) Timer/Counter 1 stopped.

SU01580

Figure 3. Timer/Counter 0/1 Mode Control (TMOD) Register

OSC

Timer n Gate bit

INTn Pin

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

÷ d*

Tn Pin

TRn

C/T = 0

C/T = 1

Control

TLn

(5 Bits)

THn

(8 Bits)

Figure 4. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter

TFn Interrupt

SU01618

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

TCON Address = 88H Reset Value = 00H

Bit Addressable

76543210

IE0IT1IE1TR0TF0TR1TF1

IT0

BIT SYMBOL FUNCTION

TCON.7 TF1 Timer 1 overflow flag. Set by hardware on T imer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on T imer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed. TCON.2 IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupts. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed. TCON.0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level

triggered external interrupts.

SU01516

OSC

Timer n Gate bit

INTn Pin

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

÷ d*

Tn Pin

TRn

Figure 5. Timer/Counter 0/1 Control (TCON) Register

C/T = 0

= 1

C/T

Control

TLn

(8 Bits)

THn

(8 Bits)

Reload

Figure 6. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload

TFn

Interrupt

SU01619

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

OSC

Timer 0 Gate bit

INT0 Pin

OSC

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

T0 Pin

÷ d*

TR0

÷ d*

TR1

C/T = 0

= 1

C/T

Control

TL0

(8 Bits)

TH0

(8 Bits)

P89C60X2/61X2

TF0

TF1

Interrupt

SU01620

Figure 7. Timer/Counter 0 Mode 3: Two 8-Bit Counters

TIMER 2 OPERATION Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T

2 in the special function register T2CON (see Figure 8). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 6.

Capture Mode

In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T

2 in T2CON) which, upon overflowing, sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2=1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 (like TF2) can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 9 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 (12-clock Mode) or osc/6 (6-clock Mode) pulses).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (C/T or down. The counting direction is determined by bit DCEN (Down

2 in T2CON), then programmed to count up

Counter Enable) which is located in the T2MOD register (see Figure 10). After reset, DCEN=0 which means Timer 2 will default to counting up. If DCEN is set, Timer 2 can count up or down depending on the value of the T2EX pin.

Figure 11 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then T imer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software.

If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.

In Figure 12 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX, Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

A logic 0 applied to pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. A Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

Table 6. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator

X X 0 (off)

T2CON Address = C8H Reset Value = 00H

Bit Addressable

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T

Symbol Position Name and Significance

TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. C/T

2 T2CON.1 Timer or counter select. (Timer 2)

CP/RL

2 T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

when either RCLK or TCLK = 1.

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

0 = Internal timer (OSC/12 in 12-clock mode or OSC/6 in 6-clock mode) 1 = External event counter (falling edge triggered).

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow .

2 CP/RL2

SU01621

2003 Sep 1 1

Figure 8. Timer/Counter 2 (T2CON) Control Register

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

OSC

T2EX Pin

*n = 6 in 6-clock mode; n = 12 in 12-clock mode.

T2 Pin

÷ n*

Transition

Detector

C/T2 = 0

C/T

EXEN2

2 = 1

TR2

Control

Capture

TL2

(8 bits)

RCAP2L RCAP2H

TH2

(8 bits)

P89C60X2/61X2

TF2

EXF2

Timer 2

Interrupt

SU01622

Figure 9. Timer 2 in Capture Mode

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

76543210

— — — — — — T2OE DCEN

Symbol Position Function

— Not implemented, reserved for future use.* T2OE T2MOD.1 Timer 2 Output Enable bit. DCEN T2MOD.0 Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down

counter.

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01519

Figure 10. Timer 2 Mode (T2MOD) Control Register

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

OSC

T2EX PIN

*n = 6 in 6-clock mode; n = 12 in 12-clock mode.

T2 Pin

÷ n*

TRANSITION

DETECTOR

C/T2 = 0

2 = 1

C/T

EXEN2

TR2

CONTROL

RELOAD

TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

P89C60X2/61X2

TF2

EXF2

TIMER 2

INTERRUPT

SU01623

OSC

*n = 6 in 6-clock mode; n = 12 in 12-clock mode.

÷ n*

T2 Pin

Figure 11. T imer 2 in Auto-Reload Mode (DCEN = 0)

(DOWN COUNTING RELOAD VALUE)

FFH FFH

C/T2 = 0

2 = 1

C/T

TL2 TH2

CONTROL

TR2

RCAP2L RCAP2H

(UP COUNTING RELOAD VALUE) T2EX PIN

OVERFLOW

Figure 12. Timer 2 Auto Reload Mode (DCEN = 1)

TOGGLE

COUNT DIRECTION 1 = UP 0 = DOWN

TF2

EXF2

INTERRUPT

SU01624

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

n = 1 in 6-clock mode n = 2 in 12-clock mode.

OSC

T2 Pin

T2EX Pin

÷ n

Transition

Detector

C/T2 = 0

C/T

2 = 1

Control

TR2

EXF2

TL2

(8 bits)

RCAP2L RCAP2H

Timer 2 Interrupt

TH2

(8 bits)

Reload

P89C60X2/61X2

Timer 1

Overflow

÷ 2

“0” “1”

“0”“1”

÷ 16

“0”“1”

÷ 16 TX Clock

SMOD

RCLK

RX Clock

TCLK

Control

EXEN2

Note availability of additional external interrupt.

Figure 13. Timer 2 in Baud Rate Generator Mode

Baud Rate Generator Mode

Bits TCLK and/or RCLK in T2CON (Table 6) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator . When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – one generated by Timer 1, the other by Timer 2.

Figure 13 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below:

Modes 1 and 3 Baud Rates +

The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T Timer operation is different for Timer 2 when it is being used as a baud rate generator.

Usually, as a timer it would increment every machine cycle (i.e., 1/6 the oscillator frequency in 6-clock mode or 1/12 the oscillator frequency in 12-clock mode). As a baud rate generator, it increments at the oscillator frequency in 6-clock mode or at 1/2 the oscillator frequency in 12-clock mode. Thus the baud rate formula is as follows:

Timer 2 Overflow Rate

2=0).

SU01625

Modes 1 and 3 Baud Rates =

Oscillator Frequency

[n [65536* (RCAP2H,RCAP2L)]]

Where:

n = 16 in 6-clock mode, 32 in 12-clock mode. (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L

taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode shown in Figure 13 is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.

When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, T imer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

Table 7 shows commonly used baud rates and how they can be obtained from Timer 2.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Table 7. Timer 2 Generated Commonly Used

Baud Rates

Baud Rate Timer 2

12-clk mode

375 K 750 K 12 MHz FF FF

9.6 K 19.2 K 12 MHz FF D9

4.8 K 9.6 K 12 MHz FF B2

2.4 K 4.8 K 12 MHz FF 64

1.2 K 2.4 K 12 MHz FE C8 300 600 12 MHz FB 1E 110 220 12 MHz F2 AF 300 600 6 MHz FD 8F 110 220 6 MHz F9 57

6-clk

mode

Summary Of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is:

Baud Rate +

If Timer 2 is being clocked internally, the baud rate is:

Baud Rate +

Where:

n = 16 in 6-clock mode, 32 in 12-clock mode. f

= Oscillator Frequency

OSC

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as:

RCAP2H,RCAP2L + 65536*

Timer 2 Overflow Rate

[n [65536* (RCAP2H,RCAP2L)]]

Osc Freq

OSC

RCAP2H RCAP2L

OSC

n Baud Rate

P89C60X2/61X2

Timer/Counter 2 Set-up

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 8 for set-up of Timer 2 as a timer. Also see Table 9 for set-up of Timer 2 as a counter.

Table 8. Timer 2 as a Timer

T2CON

MODE

16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive

and transmit same baud rate Receive only 24H 26H Transmit only 14H 16H

INTERNAL CONTROL (Note 1)

34H 36H

Table 9. Timer 2 as a Counter

MODE

16-bit 02H 0AH Auto-Reload 03H 0BH

NOTES:

1. Capture/reload occurs only on timer/counter overflow.

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.

INTERNAL CONTROL (Note 1)

EXTERNAL CONTROL (Note 2)

TMOD

EXTERNAL CONTROL (Note 2)

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

FULL-DUPLEX ENHANCED UART Standard UART operation

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.

The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs

the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency (in 12-clock mode) or 1/6 the oscillator frequency (in 6-clock mode).

Mode 1: 10 bits are transmitted (through TxD) or received

(through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable.

Mode 2: 11 bits are transmitted (through TxD) or received

(through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (in 12-clock mode) or 1/16 or 1/32 the oscillator frequency (in 6-clock mode).

Mode 3: 11 bits are transmitted (through TxD) or received

(through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

Multiprocessor Communications

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming.

P89C60X2/61X2

The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

Serial Port Control Register

The serial port control and status register is the Special Function Register SCON, shown in Figure 14. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).

Baud Rates

The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (in 12-clock mode) or / 6 (in 6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency . If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively.

Mode 2 Baud Rate =

SMOD

(Oscillator Frequency)

Where:

n = 64 in 12-clock mode, 32 in 6-clock mode

The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate.

Using Timer 1 to Generate Baud Rates

When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows:

Mode 1, 3 Baud Rate =

SMOD

(Timer 1 Overflow Rate)

Where:

n = 32 in 12-clock mode, 16 in 6-clock mode

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula:

Mode 1, 3 Baud Rate =

SMOD

Where:

n = 32 in 12-clock mode, 16 in 6-clock mode

One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 15 lists various commonly used baud rates and how they can be obtained from Timer 1.

Oscillator Frequency

12 [256–(TH1)]

2003 Sep 1 1

Philips Semiconductors Product data

SMOD

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

SCON Address = 98H Reset Value = 00H

Bit Addressable

76543210

SM0 SM1 SM2 REN TB8 RB8 TI RI

Where SM0, SM1 specify the serial port mode, as follows:

SM0 SM1 Mode Description Baud Rate

0 0 0 shift register f

/12 (12-clock mode) or f

OSC

/6 (6-clock mode)

OSC

0 1 1 8-bit UART variable 1 0 2 9-bit UART f

OSC

/64 or f

/32 (12-clock mode) or f

OSC

/32 or f

/16 (6-clock mode)

OSC

1 1 3 9-bit UART variable

SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be

activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0.

REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,

RB8 is not used.

TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other

modes, in any serial transmission. Must be cleared by software.

RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other

modes, in any serial reception (except see SM2). Must be cleared by software.

SU01626

Figure 14. Serial Port Control (SCON) Register

Baud Rate

Mode 12-clock mode 6-clock mode

OSC

C/T Mode Reload V alue

Timer 1

Mode 0 Max 1.67 MHz 3.34 MHz 20 MHz X X X X Mode 2 Max 625 k 1250 k 20 MHz 1 X X X

Mode 1, 3 Max 104.2 k 208.4 k 20 MHz 1 0 2 FFH

Mode 1, 3 19.2 k 38.4 k 11.059 MHz 1 0 2 FDH

9.6 k 19.2 k 11.059 MHz 0 0 2 FDH

4.8 k 9.6 k 11.059 MHz 0 0 2 FAH

2.4 k 4.8 k 11.059 MHz 0 0 2 F4H

1.2 k 2.4 k 11.059 MHz 0 0 2 E8H

137.5 275 11.986 MHz 0 0 2 1DH 110 220 6 MHz 0 0 2 72H 110 220 12 MHz 0 0 1 FEEBH

Figure 15. Timer 1 Generated Commonly Used Baud Rates

More About Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode).

Figure 16 shows a simplified functional diagram of the serial port in Mode 0, and associated timing.

Transmission is initiated by any instruction that uses SBUF as a destination register . The “write to SBUF” signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between “write to SBUF” and activation of SEND.

SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At

S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position.

As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after “write to SBUF.”

Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register , and in the next clock phase activates RECEIVE.

RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle.

As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set.

More About Mode 1

Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate.

Figure 17 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive.

Transmission is initiated by any instruction that uses SBUF as a destination register . The “write to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.)

The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “write to SBUF.”

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.:

1. R1 = 0, and

2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is

irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time,

P89C60X2/61X2

whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD.

More About Modes 2 and 3

Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2.

Figures 18 and 19 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode

1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF as a destination register . The “write to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.)

The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.”

At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.

1. RI = 0, and

2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is

irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Write

SBUF

REN RI

Serial

Port

Interrupt

D Q

Zero Detector

TX Control

TX Clock Send

RX Control

Start

LSB

Load SBUF

80C51 Internal Bus

SBUF

ShiftStart

1 1 1 1 1 1 1 0

Input Shift Register

ReceiveRX Clock

Shift

MSB

Shift Clock

P89C60X2/61X2

RxD

P3.0 Alt

Output

Function

TxD

P3.1 Alt

Output

Function

RxD

P3.0 Alt

Input

Function

LSB

Read SBUF

S4 . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1

ALE

Write to SBUF

Send Shift

RxD (Data Out) D0 D1 D2 D3 D4 D5 D6 D7

TxD (Shift Clock) TI

RI Receive

Shift RxD (Data In)

TxD (Shift Clock)

S6P2

S3P1 S6P1

Write to SCON (Clear RI)

D0 D1 D2 D3 D4 D5 D6

S5P2

SBUF

80C51 Internal Bus

MSB

Figure 16. Serial Port Mode 0

Transmit

Receive

SU00539

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Timer 1

SMOD = 0

Overflow

÷ 2

SMOD = 1

Write

SBUF

Serial

Port

Interrupt

÷ 16

TB8

D Q CL

TX Clock Send

÷ 16

80C51 Internal Bus

SBUF

Zero Detector

TX Control

Shift

P89C60X2/61X2

TxD

DataStart

Clock

Write to SBUF

Data Shift

TxD TI

Clock

RxD

Bit Detector Sample Times

Shift

RxD

Send

S1P1

Start Bit

÷ 16 Reset

Start Bit

1-to-0

Transition

Detector

Sample

RX Clock RI

Load SBUF

RX Control

Input Shift Register

SBUF

80C51 Internal Bus

(9 Bits)

Start

Bit Detector

Read SBUF

Figure 17. Serial Port Mode 1

Load SBUF

1FFH

Shift

Transmit

Stop BitD0 D1 D2 D3 D4 D5 D6 D7

Receive

SU00540

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

TB8

Write

Mode 2

÷ 2

Phase 2 Clock

(1/2 f

OSC

12-clock mode; f

in 6-clock

OSC

mode)

SMOD = 1

SMOD = 0 (SMOD is

PCON.7)

SBUF

1-to-0

Transition

Detector

÷ 16

Serial

Port

Interrupt

Sample

D Q CL

80C51 Internal Bus

SBUF

Zero Detector

Stop Bit

Gen.

Start

TX Clock Send

÷ 16

Start

TX Control

RX Clock

RX Control

Shift

Data

Load SBUF

1FFH

Shift

P89C60X2/61X2

TxD

Clock

Write to SBUF

Data Shift

TxD TI

Stop Bit Gen.

Clock

RxD

Bit Detector Sample Times

Shift

RxD

Send

S1P1

Start Bit

÷ 16 Reset

Start Bit

Bit Detector

Input Shift Register

(9 Bits)

Load SBUF

SBUF

Read SBUF

80C51 Internal Bus

Figure 18. Serial Port Mode 2

Shift

TB8

RB8

Transmit

Stop BitD0 D1 D2 D3 D4 D5 D6 D7

Receive

SU01627

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Timer 1

SMOD = 0

Overflow

÷ 2

SMOD = 1

Write

SBUF

Serial

Port

Interrupt

Transition

Detector

÷ 16

Sample

1-to-0

TB8

D Q CL

TX Clock Send

Start

÷ 16

Zero Detector

RX Clock

80C51 Internal Bus

SBUF

Shift

TX Control

RX Control

Load SBUF

1FFH

P89C60X2/61X2

TxD

DataStart

Shift

Clock

Write to SBUF

Data Shift

TxD TI

Stop Bit Gen.

Clock

RxD

Bit Detector Sample Times

Shift

RxD

Send

S1P1

Start Bit

÷ 16 Reset

Start Bit

Bit Detector

Input Shift Register

(9 Bits)

Load SBUF

SBUF

Read SBUF

80C51 Internal Bus

Figure 19. Serial Port Mode 3

Shift

TB8

RB8

Transmit

Stop BitD0 D1 D2 D3 D4 D5 D6 D7

Receive

SU00542

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Enhanced UART operation

In addition to the standard operation modes, the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication.

When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 20). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 21.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 22.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1101 Given = 1100 00X0

P89C60X2/61X2

Slave 1 SADDR = 1100 0000

SADEN = 1111 1110 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1001 Given = 1100 0XX0

Slave 1 SADDR = 1110 0000

SADEN = 1111 1010 Given = 1110 0X0X

Slave 2 SADDR = 1110 0000

SADEN = 1111 1100 Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 01 10. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. T o select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

SCON Address = 98H

P89C60X2/61X2

Reset Value = 0000 0000B

Bit Addressable

76543210

SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl

(SMOD0 = 0/1)*

Symbol Position Function

FE SCON.7 Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not

cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable

access to the FE bit.* SM0 SCON.7 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 SCON.6 Serial Port Mode Bit 1

SM0 SM1 Mode Description Baud Rate**

0 0 0 shift register f

/12 (12-clk mode) or f

OSC

/6 (6-clk mode)

OSC

0 1 1 8-bit UAR T variable 1 0 2 9-bit UAR T f

/64 or f

OSC

/32 (12-clock mode)

OSC

/32 or f

/16 (6-clock mode) or

OSC

1 1 3 9-bit UAR T variable

SM2 SCON.5 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set

unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or

Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was

received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN SCON.4 Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 SCON.3 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 SCON.2 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that

was received.

In Mode 0, RB8 is not used. Tl SCON.1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of

the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl SCON.0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the

stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by

NOTES:

*SMOD0 is located at PCON.6. **f

= oscillator frequency

OSC

software.

SU01628

2003 Sep 1 1

Figure 20. SCON: Serial Port Control Register

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

D0 D1 D2 D3 D4 D5 D6 D7 D8

START

BIT

SM0 / FE SM1 SM2 REN TB8 RB8 TI RI

SMOD1 SMOD0 – POF GF1 GF0 PD IDL

0 : SCON.7 = SM0 1 : SCON.7 = FE

Figure 21. UART Framing Error Detection

DATA BYTE

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

P89C60X2/61X2

ONLY IN

MODE 2, 3

SCON

(98H)

PCON

(87H)

STOP

BIT

SU01191

D0 D1 D2 D3 D4 D5 D6 D7 D8

SM0 SM1 SM2 REN TB8 RB8 TI RI

1 1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

1 0

11 X

COMPARATOR

Figure 22. UART Multiprocessor Communication, Automatic Address Recognition

SCON

(98H)

SU00045

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Interrupt Priority Structure

INT0 IT0

TF0

INT1

TF1

TF2, EXF2

IT1

Figure 23. Interrupt Sources

Interrupts

The devices described in this data sheet provide six interrupt sources. These are shown in Figure 23. The External Interrupts INT0

and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.

The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared in software.

All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (Figure 24). IE also contains a global disable bit, EA all interrupts at once.

IE0

IE1

Interrupt Sources

SU01521

, which disables

P89C60X2/61X2

Priority Level Structure

Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing bits in Special Function Registers IP (Figure 25) and IPH (Figure 26). A lower-priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same level. A high-priority level 3 interrupt can’t be interrupted by any other interrupt source.

If two request of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as follows:

Source Priority Within Level

1. IE0 (External Int 0) (highest)

2. TF0 (Timer 0)

3. IE1 (External Int 1)

4. TF1 (Timer 1)

5. RI+TI (UART)

6. TF2, EXF2 (Timer 2) (lowest) Note that the “priority within level” structure is only used to resolve

simultaneous requests of the same priority level. The IP and IPH registers contain a number of unimplemented bits.

User software should not write 1s to these positions, since they may be used in other 80C51 Family products.

How Interrupts Are Handled

The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:

1. An interrupt of equal or higher priority level is already in progress.

2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.

3. The instruction in progress is RETI or any write to the IE or IP registers.

Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to.

The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

IE Address = 0A8H

Bit Addressable

ET0EX1ET1ESET2—EA

Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it.

BIT SYMBOL FUNCTION

IE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit. IE.6 — Not implemented. Reserved for future use. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit.

Figure 24. Interrupt Enable (IE) Register

IP Address = 0B8H

Bit Addressable

PT0PX1PT1PSPT2——

Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority

BIT SYMBOL FUNCTION

IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit.

01234567

EX0

01234567

PX0

SU01523

P89C60X2/61X2

Reset Value = 0X000000B

Reset Value = xx000000B

SU01522

IPH Address = B7H

Bit Addressable

BIT SYMBOL FUNCTION

IPH.7 — Not implemented, reserved for future use. IPH.6 — Not implemented, reserved for future use. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high.

2003 Sep 1 1

Figure 25. Interrupt Priority (IP) Register

Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority

Figure 26. Interrupt Priority HIGH (IPH) Register

Reset Value = xx000000B

01234567

PT0HPX1HPT1HPSHPT2H——

PX0H

SU01524

Philips Semiconductors Product data

INTERRUPT PRIORITY LEVEL

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

. . . . . . . . .

Interrupt Latched

S5P2 S6

Interrupt

Goes

Active

. . . . . . . . .

The polling cycle/LCALL sequence is illustrated in Figure 27. Note that if an interrupt of higher priority level goes active prior to

S5P2 of the machine cycle labeled C3 in Figure 27, then in accordance with the above rules it will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed.

Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn’t. It never clears the Serial Port flag. This has to be done in the user’s software. It clears an external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as shown in Table 10.

Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off.

Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible.

External Interrupts

The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INT

x pin. If ITx = 1, external interrupt x is edge triggered. In

this mode if successive samples of the INT cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle. This is done to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt

C1 C2 C3 C4 C5

Interrupts

Are Polled

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

Figure 27. Interrupt Response Timing Diagram

x pin show a high in one

P89C60X2/61X2

. . . .

Long Call to

Interrupt

Vector Address

service routine is completed, or else another interrupt will be generated.

Response Time

The INT0

and INT1 levels are inverted and latched into IE0 and IE1 at S5P2 of every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 27 shows interrupt response timings.

A longer response time would result if the request is blocked by one of the 3 previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt’s service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more the 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV).

Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles.

As previously mentioned, the derivatives described in this data sheet have a four-level interrupt structure. The corresponding registers are IE, IP and IPH. (See Figures 24, 25, and 26.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible.

The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table:

PRIORITY BITS

IPH.x IP.x

0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority)

Interrupt Routine

SU00546

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait

interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.

P89C60X2/61X2

until it is finished before being serviced. If a lower priority level

Table 10. Interrupt Table

SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS

External interrupt 0 1 IE0 N (L)1Y (T)

Timer 0 2 TF0 Y 0BH

External interrupt 1 3 IE1 N (L) Y (T) 13H

Timer 1 4 TF1 Y 1BH

UART 5 RI, TI N 23H

Timer 2 6 TF2, EXF2 N 2BH

NOTES:

1. L = Level activated

2. T = Transition activated

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output, unless the CPU needs to perform an off-chip memory access.

The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit.

AUXR (8EH)

765432 1 0 – – – – – – EXTRAM AO

AUXR.0 AO Turns off ALE output. AUXR.1 EXTRAM Controls external data memory

access.

DPS

BIT0

AUXR1

DPH

(83H)

DPL

(82H)

DPTR1 DPTR0

Dual DPTR

The dual DPTR structure (see Figure 28) enables a way to specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a

Figure 28.

single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

•New Register Name: AUXR1#

•SFR Address: A2H

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows:

•Reset Value: xxx000x0B

AUXR1 (A2H)

76543210 – – – – GF2 0 – DPS

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg DPS

DPTR0 0 DPTR1 1

The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.

INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to

ACC

MOVX @ DPTR , A Move ACC to external RAM (16-bit

address)

JMP @ A + DPTR Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.

03H

EXTERNAL

DATA

MEMORY

SU00745A

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

Expanded Data RAM Addressing

The P89C60X2 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 byte s S pecial Func tion Register (SFR), and 256 bytes expanded RAM (ERAM) (768 bytes for the P89C61X2).

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.

4. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 29.

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only . The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example:

MOV 0A0H,#data

accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM.

P89C60X2/61X2

For example:

MOV @R0,acc

where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256/768 bytes of external data memory in the P89C60X2/61X2.

With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0,

MOVX @R0,acc

where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 30.

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.

) and P3.7 (RD).

AUXR

Symbol Function AO Disable/Enable ALE

EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR

— Not implemented, reserved for future use*.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Address = 8EH Not Bit Addressable

— —————EXTRAM AO

Bit:

AO Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 f 1 ALE is active only during off-chip memory access.

EXTRAM Operating Mode

0 Internal ERAM access using MOVX @Ri/@DPTR 1 External data memory access.

76543210

in 6-clock mode).

Figure 29. AUXR: Auxiliary Register

Reset Value = xxxx xx00B

OSC

SU01613

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

UPPER

128 BYTES

INTERNAL RAM

ERAM

256 or 768 BYTES

100

Figure 30. Internal and External Data Memory Address Space with EXTRAM = 0

HARDW ARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P89C51RA2/RB2/RC2/RD2xx)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the RST-pin (see the note below).

Using the WDT

To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is

80 80

LOWER

128 BYTES

INTERNAL RAM

P89C60X2/61X2

SPECIAL FUNCTION REGISTER

enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1h to WDTRST. WDTRST is a write only register. the WDT counter cannot be read or written. When the WDT overflows, it will generate an output RESET pulse at the reset pin (see note below). The RESET pulse duration is 98 T mode; 196 in 12-clock mode), where T best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

FFFF

0000

EXTERNAL

DATA

MEMORY

OSC

= 1/f

SU01293

. To make the

OSC

(6-clock

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

ABSOLUTE MAXIMUM RATINGS

Operating temperature under bias 0 to +70 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to V Voltage on any other pin to V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

1, 2, 3

PARAMETER

P89C60X2/61X2

RATING UNIT

0 to +13.0 V

–0.5 to +6.5 V

unless otherwise

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C

amb

CLOCK FREQUENCY

RANGE

SYMBOL FIGURE PARAMETER OPERATING MODE POWER SUPPLY

1/t

CLCL

35 Oscillator frequency

6-clock 5 V " 10% 0 20 MHz 12-clock 5 V " 10% 0 33 MHz

VOLTAGE

MIN MAX UNIT

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

DC ELECTRICAL CHARACTERISTICS

= 0 °C to +70 °C; VCC = 5 V ±10%; VSS = 0 V (20/33 MHz max. CPU clock)

amb

SYMBOL

IH1

OL1

OH1

RST

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

5. See Figures 39 through 42 for I 12-clock mode characteristics:

6. This value applies to T

7. Load capacitance for port 0, ALE, and PSEN

8. Under steady state (non-transient) conditions, I

If I test conditions.

9. ALE is tested to V

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA

11.To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0

PARAMETER TEST

LIMITS UNIT

CONDITIONS

MIN TYP1MAX

Input low voltage

4.5 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V Input high voltage (ports 0, 1, 2, 3, EA) – 0.2 VCC+0.9 VCC+0.5 V Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 3 Output low voltage, port 0, ALE, PSEN Output high voltage, ports 1, 2, 3 Output high voltage (port 0 in external bus

mode), ALE

, PSEN

– 0.7 V

VCC+0.5 V

VCC = 4.5 V; IOL = 1.6 mA2– 0.4 V

7, 8

VCC = 4.5 V; IOL = 3.2 mA2– 0.45 V

VCC = 4.5 V; IOH = –30 mA VCC = 4.5 V; IOH = –3.2 mA V

– 0.7 – V

Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –75 Logical 1-to-0 transition current, ports 1, 2, 36VIN = 2.0 V; See note 4 – –650 Input leakage current, port 0 0.45 < VIN < V

– 0.3 – ±10

Power supply current (see Figure 38): See note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped T

= 0 °C to 70°C <30 100

amb

(see Figure 42 for conditions) Programming and erase mode f

= 20MHz 60 mA

OSC

Internal reset pull-down resistor – 40 225 kΩ Pin capacitance10 (except EA) – – 15 pF

s of ALE and ports 1 and 3. The noise is due

can exceed these conditions provided that no

is approximately 2 V.

Active mode: I Idle mode: I

amb

Maximum I Maximum I Maximum total I

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

per port pin: 15 mA

per 8-bit port: 26 mA

for all outputs: 71 mA

, except when ALE is off then VOH is the voltage specification.

OH1

test conditions and Figure 38 for I

(MAX) = (8.5 + 0.62  FREQ. [MHz])mA

(MAX) = (3.5 + 0.18  FREQ. [MHz])mA

= 0°C to +70°C.

= 100 pF, load capacitance for all other outputs = 80 pF.

must be externally limited as follows:

vs. Frequency.

is 25 pF).

and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

mA mA mA

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE)

= 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V

amb

SYMBOL FIGURE PARAMETER VARIABLE CLOCK

1, 2, 3

P89C60X2/61X2

33 MHz CLOCK

MIN MAX MIN MAX UNIT

1/t t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

35 Oscillator frequency 0 33 MHz 31 ALE pulse width 2t 31 Address valid to ALE low t 31 Address hold after ALE low t 31 ALE low to valid instruction in 4t 31 ALE low to PSEN low t 31 PSEN pulse width 3t 31 PSEN low to valid instruction in 3t

–40 21 ns

CLCL

–25 5 ns

CLCL

–25 5 ns

CLCL

–65 55 ns

CLCL

–25 5 ns

CLCL

–45 45 ns

CLCL

–60 30 ns

CLCL

31 Input instruction hold after PSEN 0 0 ns 31 Input instruction float after PSEN t 31 Address to valid instruction in 5t

–25 5 ns

CLCL

–80 70 ns

CLCL

31 PSEN low to address float 10 10 ns

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

32 RD pulse width 6t 33 WR pulse width 6t 32 RD low to valid data in 5t

–100 82 ns

CLCL

–100 82 ns

CLCL

–90 60 ns

CLCL

32 Data hold after RD 0 0 ns 32 Data float after RD 2t 32 ALE low to valid data in 8t 32 Address to valid data in 9t 32, 33 ALE low to RD or WR low 3t 32, 33 Address valid to WR low or RD low 4t 33 Data valid to WR transition t 33 Data hold after WR t 33 Data valid to WR high 7t

–50 3t

CLCL

–75 45 ns

CLCL

–30 0 ns

CLCL

–25 5 ns

CLCL

–130 80 ns

CLCL

–28 32 ns

CLCL

–150 90 ns

CLCL

–165 105 ns

CLCL

+50 40 140 ns

CLCL

32 RD low to address float 0 0 ns 32, 33 RD or WR high to ALE high t

CLCL

–25 t

+25 5 55 ns

CLCL

External Clock

CHCX

CLCX

CLCH

CHCL

35 High time 17 t 35 Low time 17 t

CLCL–tCLCX CLCL–tCHCX

35 Rise time 5 ns 35 Fall time 5 ns

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

34 Serial port clock cycle time 12t 34 Output data setup to clock rising edge 10t 34 Output data hold after clock rising edge 2t

CLCL

–133 167 ns

CLCL

–80 50 ns

CLCL

360 ns

34 Input data hold after clock rising edge 0 0 ns 34 Clock rising edge to input data valid 10t

–133 167 ns

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

ns ns

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE)

= 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V

amb

SYMBOL

FIGURE

PARAMETER VARIABLE CLOCK

1, 2, 3

P89C60X2/61X2

20 MHz CLOCK

MIN MAX MIN MAX UNIT

1/t t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

35 Oscillator frequency 0 20 MHz 31 ALE pulse width t 31 Address valid to ALE low 0.5t 31 Address hold after ALE low 0.5t 31 ALE low to valid instruction in 2t 31 ALE low to PSEN low 0.5t 31 PSEN pulse width 1.5t 31 PSEN low to valid instruction in 1.5t

–40 10 ns

CLCL

–20 5 ns

CLCL

–20 5 ns

CLCL

–65 35 ns

CLCL

–20 5 ns

CLCL

–45 30 ns

CLCL

–60 15 ns

CLCL

31 Input instruction hold after PSEN 0 0 ns 31 Input instruction float after PSEN 0.5t 31 Address to valid instruction in 2.5t

–20 5 ns

CLCL

–80 45 ns

CLCL

31 PSEN low to address float 10 10 ns

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

32 RD pulse width 3t 33 WR pulse width 3t 32 RD low to valid data in 2.5t

–100 50 ns

CLCL

–100 50 ns

CLCL

–90 35 ns

CLCL

32 Data hold after RD 0 0 ns 32 Data float after RD t 32 ALE low to valid data in 4t 32 Address to valid data in 4.5t 32, 33 ALE low to RD or WR low 1.5t 32, 33 Address valid to WR low or RD low 2t 33 Data valid to WR transition 0.5t 33 Data hold after WR 0.5t 33 Data valid to WR high 3.5t

–50 1.5t

CLCL

–75 25 ns

CLCL

–25 0 ns

CLCL

–20 5 ns

CLCL

–130 45 ns

CLCL

–20 5 ns

CLCL

–150 50 ns

CLCL

–165 60 ns

CLCL

+50 25 125 ns

CLCL

32 RD low to address float 0 0 ns 32, 33 RD or WR high to ALE high 0.5t

CLCL

–20 0.5t

+20 5 45 ns

CLCL

External Clock

CHCX

CLCX

CLCH

CHCL

35 High time 20 t 35 Low time 20 t

CLCL–tCLCX CLCL–tCHCX

35 Rise time 5 ns 35 Fall time 5 ns

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

34 Serial port clock cycle time 6t 34 Output data setup to clock rising edge 5t 34 Output data hold after clock rising edge t

CLCL

–133 117 ns

CLCL

–30 20 ns

CLCL

300 ns

34 Input data hold after clock rising edge 0 0 ns 34 Clock rising edge to input data valid 5t

–133 117 ns

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

ns ns

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE

ALE

PSEN

PORT 0

LHLL

AVLL

LLPL

LLAX

A0–A7 A0–A7

LLIV

PLIV

PLPH

PLAZ

PXIX

P – PSEN Q – Output data R–RD

signal t – Time V – Valid W– WR

signal X – No longer a valid logic level Z – Float

INSTR IN

Examples: t

PXIZ

= Time for address valid to ALE low.

AVLL

LLPL

P89C60X2/61X2

=Time for ALE low to PSEN low.

ALE

PSEN

PORT 0

PORT 2

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

AVIV

A0–A15 A8–A15

Figure 31. External Program Memory Read Cycle

WHLH

LLDV

LLWL

RLAZ

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

RLDV

RLRH

RHDZ

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

SU00006

2003 Sep 1 1

SU00025

Figure 32. External Data Memory Read Cycle

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

ALE

PSEN

LLWL

LLAX

A0–A7

FROM RI OR DPL

AVWL

QVWX

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

PORT 0

PORT 2

AVLL

P89C60X2/61X2

WHLH

WLWH

WHQX

QVWH

DATA OUT A0–A7 FROM PCL INSTR IN

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

SU00026

Figure 33. External Data Memory Write Cycle

012345678

XLXL

QVXH

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHQX

1230 4567

XHDX

SET TI

SET RI

SU00027

Figure 34. Shift Register Mode Timing

VCC–0.5

0.45V

0.7V

0.2VCC–0.1

CHCL

CLCX

CLCL

CHCX

CLCH

SU00009

Figure 35. External Clock Drive

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

VCC–0.5

0.45V

NOTE:

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

Figure 36. AC Testing Input/Output

0.2V

+0.9

–0.1

0.2V

SU00717

P89C60X2/61X2

+0.1V

NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V

OH/VOL

LOAD

–0.1V

LOAD

level occurs. IOH/IOL ≥ ±20mA.

TIMING

REFERENCE

POINTS

Figure 37. Float Waveform

SU00718

–0.1V

+0.1V

(mA)

P89C60X2/61X2

4 8 12 16 20 24 28 32 36

MAXIMUM ICC ACTIVE

TYPICAL ICC ACTIVE

MAXIMUM IDLE

TYPICAL IDLE

Frequency at XTAL1 (MHz, 12-clock mode)

SU01675

Figure 38. ICC vs. FREQ for 12-clock operation

Valid only within frequency specifications

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

SU00719

0.7V

0.2VCC–0.1

CHCL

RST

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

Figure 39. ICC Test Condition, Active Mode

All other pins are disconnected

Figure 41. Clock Signal Waveform for ICC Tests in Active and Idle Modes

VCC–0.5

0.45V

CLCH

= t

CLCX

CHCL

CLCL

= 5ns

P89C60X2/61X2

RST

(NC)

CLOCK SIGNAL

Figure 40. ICC Test Condition, Idle Mode

All other pins are disconnected

CHCX

CLCH

SU00009

XTAL2

XTAL1 V

P0 EA

SU00720

SU00016

(NC)

RST

XTAL2

XTAL1

Figure 42. ICC Test Condition, Power Down Mode

All other pins are disconnected. V

= 2 V to 5.5 V

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

P89C60X2/61X2

2003 Sep 1 1

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

P89C60X2/61X2

REVISION HISTORY

Rev Date Description

_2 20030911 Preliminary data (9397 750 11927); ECN 853-2400 30250 of 25 August 2003

Modifications:

•Added Watchdog Timer feature

•Added DIP40 package

_1 20020723 Preliminary data (9397 750 10131)

Data sheet status

Product

Level

III

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Data sheet status

Objective data

Preliminary data

Product data

http://www.semiconductors.philips.com.

[1]

[2] [3]

status

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit http://www.semiconductors.philips.com . Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Document order number: 9397 750 11927

 Koninklijke Philips Electronics N.V. 2003

Date of release: 09-03

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2003 Sep 1 1

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Datasheet P89C60X2, P89C61X2 Datasheet (Philips)

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