Philips P89C60X2, P89C61X2 Technical data

P89C60X2

INTEGRATED CIRCUITS

P89C60X2/61X2

80C51 8-bit Flash microcontroller family

64KB Flash 512B/1024B RAM

Product data	2003 Sep 11
Supersedes data of 2002 Jul 23

P s

on o s

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

DESCRIPTION

The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs. They are manufactured in an advanced CMOS process and contain a non-volatile Flash program memory that is programmable in parallel (via a parallel programmer) or In-System Programmable (ISP) via boot loader. They support both 12-clock and 6-clock operation.

The P89C60X2 and P89C61X2 contain 512 bytes RAM and 1024 bytes RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.

In addition, the devices are static designs which offer a wide range of operating frequencies down to zero. Two software selectable modes of power reduction Ð idle mode and power-down mode Ð are available. The idle mode freezes the CPU while allowing the

RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped.

SELECTION TABLE

For applications requiring more RAM, as well as more on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets.

Type

Memory

Timers

Serial Interfaces

ADCbits/ch.

RAM

ROM

OTP

Flash

of# Timers

PWM

PCA

WD

UART

I

CAN

SPI

I/OPins

Interrupts (External)

C

2

P89C60X2

512B

±

±

64K

3

±

±

n

n

±

±

±

±

32

6 (2)

P89C61X2

1024B

±

±

64K

3

±

±

n

n

±

±

±

±

32

6 (2)

NOTE:

		DefaultClock Rate	Optional ClockRate	Max.
	Program Security			Freq.
				at 6-clk
				/ 12-clk
				(MHz)
	n	12±clk	6-clk	20/33
	n	12±clk	6-clk	20/33

Freq.	Freq.
Range	Range
at 3V	at 5V
(MHz)	(MHz)

±0±20/33

±0±20/33

1.I2C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;

ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation

2003 Sep 11

2

853-2400 30250

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

FEATURES

•80C51 Central Processing Unit

±64 kbytes Flash

±512 bytes RAM (P89C60X2)

±1024 bytes RAM (P89C61X2)

±Boolean processor

±Fully static operation

•In-System Programmable (ISP) Flash memory

•12-clock operation with selectable 6-clock operation (via software or via parallel programmer)

•Memory addressing capability

± Up to 64 kbytes ROM and 64 kbytes RAM

•Power control modes:

±Clock can be stopped and resumed

±Idle mode

±Power-down mode

•Two speed ranges

±0 to 20 MHz with 6-clock operation

±0 to 33 MHz with 12-clock operation

•LQFP, PLCC, and DIP packages

•Dual Data Pointers

•Three security bits

•Four interrupt priority levels

•Six interrupt sources

•Four 8-bit I/O ports

•Full-duplex enhanced UART

±Framing error detection

±Automatic address recognition

•Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)

•Programmable clock-out pin

•Watchdog timer

•Asynchronous port reset

•Low EMI (inhibit ALE, 6-clock mode)

•Wake-up from Power Down by an external interrupt

2003 Sep 11

3

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

P89C60X2 ORDERING INFORMATION

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C60X2BA/00	PLCC44	plastic leaded chip carrier; 44 leads	SOT187-2	0 to +70
P89C60X2BN/00	DIP40	plastic dual in-line package; 40 leads	SOT129-1	0 to +70
P89C60X2BBD/00	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70

P89C61X2 ORDERING INFORMATION

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C61X2BA/00	PLCC44	plastic lead chip carrier; 44 leads	SOT187-2	0 to +70
P89C61X2BN/00	DIP40	plastic dual in-line package; 40 leads	SOT129-1	0 to +70
P89C61X2BBD/00	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70

PART NUMBER DERIVATION

Memory								Temperature Range	Package
	P89C60X2							B = 0 °C to +70 °C	A = PLCC
							X2 = 6-clock		BD = LQFP
	9 = Flash				0 =	512 bytes RAM
						64 kbytes FLASH	mode available
					1=	1024 bytes RAM
						64 kbytes FLASH

The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:

Operating Mode	Power Supply	Maximum Clock Frequency
6-clock	5 V ± 10%	20 MHz
12-clock	5 V ± 10%	33 MHz

2003 Sep 11

4

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

BLOCK DIAGRAM 1

		ACCELERATED 80C51 CPU
		(12-CLK MODE, 6-CLK MODE)
	64 KBYTE
	CODE FLASH
		FULL-DUPLEX
		ENHANCED UART
	512 / 1024 BYTE
	DATA RAM
		TIMER 0
		TIMER 1
	PORT 3
	CONFIGURABLE I/Os
		TIMER 2
	PORT 2
	CONFIGURABLE I/Os
		WATCHDOG
	PORT 1	TIMER
	CONFIGURABLE I/Os
	PORT 0
	CONFIGURABLE I/Os
CRYSTAL OR	OSCILLATOR
RESONATOR
		su01664
2003 Sep 11		5

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

BLOCK DIAGRAM 2 (CPU-ORIENTED)

				P0.0±P0.7	P2.0±P2.7
				PORT 0	PORT 2
				DRIVERS	DRIVERS
VCC
VSS
	RAM ADDR		RAM	PORT 0	PORT 2	FLASH
	REGISTER			LATCH	LATCH
							8
	B		ACC			STACK
	REGISTER					POINTER
							PROGRAM
					TMP1		ADDRESS
				TMP2			REGISTER
				ALU			BUFFER
					SFRs
					TIMERS		PC
				PSW			INCRE-
							MENTER
						8	16
							PROGRAM
							COUNTER
PSEN		INSTRUCTION	REGISTER
ALE/PROG	TIMING						DPTR'S
EA / VPP	AND						MULTIPLE
	CONTROL
RST
	PD			PORT 1		PORT 3
				LATCH		LATCH
	OSCILLATOR
				PORT 1		PORT 3
				DRIVERS		DRIVERS
	XTAL1		XTAL2
				P1.0±P1.7		P3.0±P3.7
							SU01671
2003 Sep 11					6

Philips Semiconductors

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

LOGIC SYMBOL
		VCC	VSS
		XTAL1
			0	ADDRESS AND
			PORT	DATA BUS
		XTAL2
				T2
			1	T2EX
		RST
			PORT
		EA/VPP
		PSEN
FUNCTIONSSECONDARY	ALE/PROG		2PORT
	RxD	3PORT
	TxD
	INT0
	INT1			ADDRESS BUS
	T0
	T1
	WR
	RD
				SU01672

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

6	1	40
7		39
	PLCC
17		29
18		28

Pin	Function			Pin	Function				Pin	Function
1	NIC*			16	P3.4/T0				31	P2.7/A15
2	P1.0/T2			17	P3.5/T1				32
										PSEN
3	P1.1/T2EX			18					33	ALE
					P3.6/WR
4	P1.2			19					34	NIC*
					P3.7/RD
5	P1.3			20	XTAL2				35
										EA/VPP
6	P1.4			21	XTAL1				36	P0.7/AD7
7	P1.5			22	VSS				37	P0.6/AD6
8	P1.6			23	NIC*				38	P0.5/AD5
9	P1.7			24	P2.0/A8				39	P0.4/AD4
10	RST			25	P2.1/A9				40	P0.3/AD3
11	P3.0/RxD			26	P2.2/A10				41	P0.2/AD2
12	NIC*			27	P2.3/A11				42	P0.1/AD1
13	P3.1/TxD			28	P2.4/A12				43	P0.0/AD0
14				29	P2.5/A13				44	VCC
	P3.2/INT0
15				30	P2.6/A14
	P3.3/INT1

* NO INTERNAL CONNECTION	SU01062

Product data

P89C60X2/61X2

LOW PROFILE QUAD FLAT PACK

PIN FUNCTIONS

						44								34
	1																		33
											LQFP
	11																		23
						12								22
Pin	Function							Pin			Function							Pin		Function
1	P1.5					16					VSS			31						P0.6/AD6
2	P1.6					17					NIC*			32						P0.5/AD5
3	P1.7					18					P2.0/A8			33						P0.4/AD4
4	RST					19					P2.1/A9			34						P0.3/AD3
5	P3.0/RxD					20					P2.2/A10			35						P0.2/AD2
6	NIC*					21					P2.3/A11			36						P0.1/AD1
7	P3.1/TxD					22					P2.4/A12			37						P0.0/AD0
8						23					P2.5/A13			38						VCC
	P3.2/INT0
9						24					P2.6/A14			39						NIC*
	P3.3/INT1
10	P3.4/T0					25					P2.7/A15			40						P1.0/T2
11	P3.5/T1					26								41						P1.1/T2EX
											PSEN
12						27					ALE			42						P1.2
	P3.6/WR
13						28					NIC*			43						P1.3
	P3.7/RD
14	XTAL2					29								44						P1.4
											EA/VPP
15	XTAL1					30					P0.7/AD7

* NO INTERNAL CONNECTION	SU01487

PLASTIC DUAL IN-LINE PACKAGE PIN FUNCTIONS

	T2/P1.0								VCC
			1				40
T2EX/P1.1
			2				39		P0.0/AD0
		P1.2	3				38		P0.1/AD1
		P1.3	4				37		P0.2/AD2
		P1.4	5				36		P0.3/AD3
		P1.5	6				35		P0.4/AD4
		P1.6	7				34		P0.5/AD5
		P1.7	8				33		P0.6/AD6
		RST	9				32		P0.7/AD7
					DUAL
	RxD/P3.0		10				31		EA/VPP
				IN-LINE
	TxD/P3.1		11	PACKAGE			30
									ALE/PROG
			12				29
	INT0/P3.2								PSEN
			13				28		P2.7/A15
	INT1/P3.3
	T0/P3.4		14				27		P2.6/A14
	T1/P3.5		15				26		P2.5/A13
			16				25		P2.4/A12
	WR/P3.6
			17				24		P2.3/A11
	RD/P3.7
	XTAL2		18				23		P2.2/A10
	XTAL1		19				22		P2.1/A9
		VSS	20				21		P2.0/A8

SU01780

2003 Sep 11

7

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

PLCC

DIP

LQFP

TYPE

NAME AND FUNCTION

VSS

22

20

16

I

Ground: 0 V reference.

VCC

44

40

38

I

Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

P0.0-0.7

43±36

39±32

37±30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory.

In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs

the code bytes during program verification and received code bytes during Flash

programming. External pull-ups are required during program verification.

P1.0±P1.7

2±9

1±8

40±44,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have

1±3

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 1 pins that are externally pulled low will source current because of the

internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the

low-order address byte during program memory verification. Alternate functions for Port 1

include:

2

1

40

I/O

T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable

Clock-Out)

3

2

41

I

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control

P2.0±P2.7

24±31

21±28

18±25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 2 pins that are externally being pulled low will source current because of the

internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order

address byte during fetches from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it

uses strong internal pull-ups when emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function

register. Some Port 2 pins receive the high order address bits during Flash programming

and verification.

P3.0±P3.7

11,

10±17

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have

13±19

7±13

1s written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 3 pins that are externally being pulled low will source current because of the

pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features

of the 80C51 family, as listed below:

11

10

5

I

RxD (P3.0): Serial input port

13

11

7

O

TxD (P3.1): Serial output port

14

12

8

I

(P3.2): External interrupt

INT0

15

13

9

I

(P3.3): External interrupt

INT1

16

14

10

I

T0 (P3.4): Timer 0 external input

17

15

11

I

T1 (P3.5): Timer 1 external input

18

16

12

O

(P3.6): External data memory write strobe

WR

19

17

13

O

(P3.7): External data memory read strobe

RD

RST

10

9

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to VSS permits a power-on reset using only an

external capacitor to VCC.

ALE/PROG

33

30

27

O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (12-clk) or 1/3 (6-clk Mode) the oscillator frequency, and can be used

for external timing or clocking. Note that one ALE pulse is skipped during each access to

external data memory. This pin is also the program pulse input

(PROG)

during Flash

programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will

be active only during a MOVX instruction.

32

29

26

O

Program Store Enable: The read strobe to external program memory. When the device

PSEN

is executing code from the external program memory,

PSEN

is activated twice each

machine cycle, except that two

PSEN

activations are skipped during each access to

external data memory.

PSEN

is not activated during fetches from internal program

memory.

35

31

29

I

External Access Enable/Programming Supply Voltage:

must be externally held low to enable the

EA/VPP

EA

device to fetch code from external program memory locations 0000H to FFFFH. If

EA

is held high, the device

executes from internal program memory. This pin also receives the 5 V / 12 V programming supply voltage

(VPP) during Flash programming. If security bit 1 is programmed,

EA

will be internally latched on Reset.

2003 Sep 11

8

Philips Semiconductors Product data

80C51 8-bit Flash microcontroller family						P89C60X2/61X2
64KB Flash, 512B/1024B RAM
	PIN NUMBER
MNEMONIC	PLCC	DIP	LQFP	TYPE	NAME AND FUNCTION
XTAL1	21	19	15	I	Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
					generator circuits.
XTAL2	20	18	14	O	Crystal 2: Output from the inverting oscillator amplifier.
NOTE:						+ 0.5 V or V		± 0.5 V, respectively.
To avoid ªlatch-upº effect at power-on, the voltage on any pin at any time must not be higher than V							SS
					CC

2003 Sep 11

9

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

SPECIAL FUNCTION REGISTERS (see notes on next page)

SYMBOL

DESCRIPTION

DIRECT

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

ADDRESS

MSB

LSB

VALUE

ACC*

Accumulator

E0H

E7

E6

E5

E4

E3

E2

E1

E0

00H

AUXR#

Auxiliary

8EH

±

±

±

±

±

±

EXTRAM

AO

xxxxxx00B

AUXR1#

Auxiliary 1

A2H

xxx000x0B

±

±

±

±

GF2

0

±

DPS

B*

B register

F0H

00H

F7

F6

F5

F4

F3

F2

F1

F0

CKCON

Clock Control Register

8FH

x0xxxxx0B

±

WDX2

±

±

±

±

±

X2

DPTR:

Data Pointer (2 bytes)

DPH

Data Pointer High

83H

00H

DPL

Data Pointer Low

82H

00H

AF

AE

AD

AC

AB

AA

A9

A8

IE*

Interrupt Enable

A8H

0x000000B

EA

±

ET2

ES

ET1

EX1

ET0

EX0

BF

BE

BD

BC

BB

BA

B9

B8

IP*

Interrupt Priority

B8H

xx000000B

±

±

PT2

PS

PT1

PX1

PT0

PX0

IPH#

Interrupt Priority High

B7H

xx000000B

±

±

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

87

86

85

84

83

82

81

80

P0*

Port 0

80H

FFH

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

97

96

95

94

93

92

91

90

P1*

Port 1

90H

FFH

±

±

±

±

±

±

T2EX

T2

A7

A6

A5

A4

A3

A2

A1

A0

P2*

Port 2

A0H

FFH

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

B7

B6

B5

B4

B3

B2

B1

B0

P3*

Port 3

B0H

FFH

RD

WR

T1

T0

INT1

INT0

TxD

RxD

PCON#1

Power Control

87H

00xx0000B

SMOD1

SMOD0

±

POF

GF1

GF0

PD

IDL

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

000000x0B

CY

AC

F0

RS1

RS0

OV

±

P

RACAP2H#

Timer 2 Capture High

CBH

00H

RACAP2L#

Timer 2 Capture Low

CAH

00H

SADDR#

Slave Address

A9H

00H

SADEN#

Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

98

SCON*

Serial Control

98H

00H

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

SP

Stack Pointer

81H

07H

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer Control

88H

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

CF

CE

CD

CC

CB

CA

C9

C8

T2CON*

Timer 2 Control

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

00H

T2MOD#

Timer 2 Mode Control

C9H

±

±

±

±

±

±

T2OE

DCEN

xxxxxx00B

TH0

Timer High 0

8CH

00H

TH1

Timer High 1

8DH

00H

TH2#

Timer High 2

CDH

00H

TL0

Timer Low 0

8AH

00H

TL1

Timer Low 1

8BH

00H

TL2#

Timer Low 2

CCH

00H

TMOD

Timer Mode

89H

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

WDTRST

Watchdog Timer Reset

A6H

2003 Sep 11

10

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

NOTES:

Special Function Registers (SFRs) accesses are restricted in the following ways:

1.Do not attempt to access any SFR locations not defined.

2.Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

3.SFR bits labeled `±', `0' or `1' can ONLY be written and read as follows:

`±' MUST be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives.

`0' MUST be written with `0', and will return a `0' when read.

`1' MUST be written with `1', and will return a `1' when read.

*: SFRs are bit addressable.

#: SFRs are modified from or added to the 80C51 SFRs.

±: Reserved bits (see note above).

1: Reset value depends on reset source.

2003 Sep 11

11

Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

FLASH EPROM MEMORY

GENERAL DESCRIPTION

The P89C60X2/61X2 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming (ISP) and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface.

The P89C60X2/61X2 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C60X2/61X2 uses a +5 V VPP supply to perform the Program/Erase algorithms (12 V tolerant).

•Programmable security for the code in the Flash.

•10,000 minimum erase/program cycles for each byte.

•10-year minimum data retention.

FLASH PROGRAMMING AND ERASURE

There are two methods of erasing or programming of the Flash memory that may be used. First, the on-chip ISP boot loader may be invoked. Second, the Flash may be programmed or erased using parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices.

FEATURES

•Flash EPROM internal program memory with Block Erase.

•Internal 1-kbyte fixed BootROM, containing low-level in-system programming routines and a default serial loader.

•Loader in BootROM allows in-system programming via the serial port.

•Up to 64 kbytes external program memory if the internal program memory is disabled (EA = 0).

•Programming and erase voltage +5 V (+12 V tolerant).

•Read/Programming/Erase using ISP:

±Byte Programming (8 ms).

±Typical erase times:

Block Erase (4 kbytes) in 3 seconds. Full-chip erase in 15 seconds.

•Parallel programming with 87C51 compatible hardware interface to programmer.

FLASH MEMORY CHARACTERISTICS

Flash User Code Memory Organization

The P89C60X2/61X2 contains 64 kbytes Flash user code program memory organized into 4-kbyte blocks (see Figure 1).

Boot ROM

When the microcontroller programs its Flash memory during ISP, all of the low level details are handled by code that is contained in a

1 kbyte BootROM. BootROM operations include: erase block, program byte, verify byte, program security bit, etc.

Clock Mode

The clock mode feature sets operating frequency to be 1/12 or 1/6 of the oscillator frequency. The clock mode configuration bit, FX2, is located in the Security Block (See Table 1). FX2, when programmed, will override the SFR clock mode bit (X2) in the CKCON register. If FX2 is erased, then the SFR bit (X2) may be used to select between 6-clock and 12-clock mode.

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

Table 1.

CLOCK MODE CONFIG BIT (FX2)						X2 bit in CKCON				DESCRIPTION
erased						0				12-clock mode (default)
erased						1				6-clock mode
programmed						x				6-clock mode
NOTE:
1. Default clock mode after ChipErase is set to 12-clock.
							FFFF
								BLOCK 15		BOOT ROM
								BLOCK 14		(1 kB)
								BLOCK 13
	P89C60X2
								BLOCK 12
	P89C61X2
							C000
								BLOCK 11
								BLOCK 10
						PROGRAM
								BLOCK 9
						ADDRESS
								BLOCK 8
	8000
								BLOCK 7
								BLOCK 6		Each block is
										4 kbytes in size
								BLOCK 5
	4000							BLOCK 4
								BLOCK 3
	2000							BLOCK 2
								BLOCK 1
					0000			BLOCK 0
										SU01673

Figure 1. Flash Memory Configuration

Power-On Reset Code Execution

The P89C60X2/61X2 contains a special Flash register, the STATUS

BYTE. At the falling edge of reset, the P89C60X2/61X2 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Status Byte is set to a value other than zero, the factory masked-ROM ISP boot loader is invoked. The factory default for the Status Byte is FFh. Once set to 00h, the Status Byte can only be changed back to FFh by a full-chip erase operation when using ISP.

Hardware Activation of the Boot Loader

The boot loader can also be executed by holding PSEN LOW,

EA greater than VIH (such as +5 V), and ALE HIGH (or not connected) at the falling edge of RESET. This is the same effect as having a non-zero status byte. This allows an application to be built that will normally execute the end user's code but can be manually forced into ISP operation.

After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

VCC

	VPP
RST	VCC
XTAL2	TxD
	RxD

P89C60X2

P89C61X2

XTAL1

VSS

+5 V (+12 V tolerant)

+5 V

TxD

RxD

VSS

SU01674

Figure 2. In-System Programming with a Minimum of Pins

In-System Programming (ISP)

:NNAAAARRDD..DDCC<crlf>

The In-System Programming (ISP) is performed without removing the microcontroller from the system. The In-System Programming

(ISP) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89C60X2/61X2 through the serial port. This firmware is provided by Philips and embedded within each P89C60X2/61X2 device.

The Philips In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

The ISP function uses five pins: TxD, RxD, VSS, VCC, and VPP (see

Figure 2). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. The VPP supply should be adequately decoupled and VPP not allowed to exceed datasheet limits.

Free ISP software is available from the Embedded Systems Academy: ªFlashMagicº

1.Direct your browser to the following page: http://www.esacademy.com/software/flashmagic/

2.Download Flashmagic

3.Execute ªflashmagic.exeº to install the software

Using the In-System Programming (ISP)

The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89C60X2/61X2 to establish the baud rate. The ISP firmware provides auto-echo of received characters.

Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:

In the Intel Hex record, the ªNNº represents the number of data bytes in the record. The P89C60X2/61X2 will accept up to 16 (10H) data bytes. The ªAAAAº string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000. The ªRRº string indicates the record type. A record type of ª00º is a data record. A record type of ª01º indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 16

(decimal). ISP commands are summarized in Table 2.

As a record is received by the P89C60X2/61X2, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89C60X2/61X2 will send an ªXº out the serial port indicating a checksum error. If the checksum calculation

is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a ª.º character out the serial port (displaying the contents of the internal program memory is an exception).

In the case of a Data Record (record type 00), an additional check is made. A ª.º character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record, an ªXº indicates that the checksum failed to match, and an ªRº character indicates that one of the bytes did not properly program. It is necessary to send a type 02 record (specify oscillator frequency) to the P89C60X2/61X2 before programming data.

The ISP facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. The user thus needs to provide the P89C60X2/61X2 with information required to generate the proper timing. Record type 02 is provided for this purpose.

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

Table 2. Intel-Hex Records Used by In-System Programming

RECORD TYPE			COMMAND/DATA FUNCTION
00	Program Data
	:nnaaaa00dd....ddcc
	Where:
	nn	= number of bytes (hex) in record
	aaaa	= memory address of first byte in record
	dd....dd	= data bytes
	cc	= checksum
	Example:
	:10008000AF5F67F0602703E0322CFA92007780C3FD
01	End of File (EOF), no operation
	:xxxxxx01cc
	Where:
	xxxxxx	= required field, but value is a ªdon't careº
	cc	= checksum
	Example:
	:00000001FF
03	Miscellaneous Write Functions
	:nnxxxx03ffssddcc
	Where:
	nn	= number of bytes (hex) in record
	xxxx	= required field, but value is a ªdon't careº
	03	= Write Function
	ff	= subfunction code
	ss	= selection code
	dd	= data input (as needed)
	cc	= checksum
	Subfunction Code = 04 (Set Status Byte to 00h)
	ff = 04
	ss = don't care
	Example:
	:020000030400F7		set status byte to 00h (device executes user code after Reset)
	Subfunction Code = 05 (Program Security Bits)
	ff = 05
	ss = 00 program security bit 1			(inhibit writing to Flash)
	01 program security bit 2			(inhibit Flash verify)
	02 program security bit 3			(disable external memory)
	Example:
	:020000030501F5		program security bit 2
	Subfunction Code = 06 (Program Flash X2 bit)
	ff = 06
	ss = 02 program FX2 bit (dd = 80) 6±clk. mode enabled
	dd = data
	Example 1:
	:0300000306028072		program FX2 bit (enable 6±clk. mode)

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

RECORD TYPE			COMMAND/DATA FUNCTION
03 (cont.)	Subfunction Code = 07 (Full Chip Erase)
	Erases all blocks, security bits, and sets status byte to default values
	ff = 07
	ss = don't care
	dd = don't care
	Example:
	:0100000307F5 full chip erase
	Subfunction Code = 0C (Erase 4k blocks)
	ff = 0C
	ss = block code as shown below:
		block 0, 0k ~ 4k, 00H
		block 1, 4k ~ 8k, 10H
		block 2, 8k ~ 12k, 20H
		block 3, 12k ~ 16k, 30H
		block 4, 16k ~ 20k, 40H
		block 5, 20k ~ 24k, 50H
		block 6, 24k ~ 28k, 60H
		block 7, 28k ~ 32k, 70H
		block 8, 32k ~ 36k, 80H
		block 9, 36k ~ 40k, 90H
		block 10, 40k ~ 44k, A0H
		block 11, 44k ~ 48k, B0H
		block 12, 48k ~ 52k, C0H
		block 13, 52k ~ 56k, D0H
		block 14, 56k ~ 60k, E0H
	Example:	block 15, 60k ~ 64k, F0H
	:020000030C20CF erase 4k block 2
04	Display Device Data or Blank Check ± Record type 04 causes the contents of the entire Flash array to be sent out
	the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that
	address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is
	initiated by the reception of any character and terminated by the reception of any character.
	General Format of Function 04
	:05xxxx04sssseeeeffcc
	Where:
	05	= number of bytes (hex) in record
	xxxx	= required field, but value is a ªdon't careº
	04	= ªDisplay Device Data or Blank Checkº function code
	ssss	= starting address
	eeee	= ending address
	ff	= subfunction
		00 = display data
		01 = blank check
		02 = display data in data block (valid addresses: 0001 ~ 0FFFH)
	cc	= checksum
	Example 1:
	:0500000440004FFF0069		display 4000±4FFF
	Example 2:
	:0500000400000FFF02E7		display data in data block (the data at address 0000 is
			invalid)

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

RECORD TYPE			COMMAND/DATA FUNCTION
05	Miscellaneous Read Functions
	General Format of Function 05
	:02xxxx05ffsscc
	Where:
	02	=	number of bytes (hex) in record
	xxxx	=	required field, but value is a ªdon't careº
	05	=	ªMiscellaneous Readº function code
	ffss	=	subfunction and selection code
			0000 = read signature byte ± manufacturer id (15H)
			0001 = read signature byte ± device id # 1	(C2H)
			0002 = read signature byte ± device id # 2
			P89C60X2 = EFh
			P89C61X2 = F0h
			0003 = read FX2 bit
			0080 = read ROM code revision
			0700 = read security bits
			0701 = read status byte
	cc	= checksum
	Example 1:
	:020000050001F8 read signature byte ± device id # 1
	Example 2:
	:020000050003F6 read FX2 bit (bit 7 = 0 represents 12-clk mode, bit 7 = 1
	Example 3:		represents 6-clk mode)
	:02000005008079 read ROM code revision (0A: Rev. A; 0B: Rev. B, etc.)
06	Direct Load of Baud Rate
	General Format of Function 06
	:02xxxx06hhllcc
	Where:
	02	=	number of bytes (hex) in record
	xxxx	=	required field, but value is a ªdon't careº
	06	=	ºDirect Load of Baud Rateº function code
	hh	=	high byte of Timer 2
	ll	=	low byte of Timer 2
	cc	=	checksum
	Example:
	:02000006F500F3

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Philips Semiconductors Product data

	80C51 8-bit Flash microcontroller family	P89C60X2/61X2
	64KB Flash, 512B/1024B RAM

Security

The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The P89C60X2/61X2 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 3). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1.

Table 3.

	SECURITY LOCK BITS1	PROTECTION DESCRIPTION
	Level
	LB1	MOVC instructions executed from external program memory are disabled from fetching code bytes from
		internal memory.
	LB2	Program verification is disabled
	LB3	External execution is disabled.

NOTE:

1. The security lock bits are independent.

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