Philips P87C51MB2, P87C51MC2 Technical data

INTEGRATED CIRCUITS

USER’S MANUAL

P87C51MB2/P87C51MC2

80C51 8-bit microcontroller family with extended memory

64KB/96KB OTP with 2KB/3KB RAM

Preliminary

2002 June 28

Version 0.95

Philips

Semiconductors

Philips Semiconductors				P87C51Mx2 User Manual
	Extended Address Range Microcontroller			P87C51Mx2
1	INTRODUCTION ............................................................................................................................			1
	1.1	The 51MX CPU CORE ..........................................................................................................		1
	1.2	P87C51Mx2 microcontrollers.................................................................................................		1
	1.3	P87C51Mx2 Logic Symbol ....................................................................................................		3
	1.4	P87C51Mx2 Block Diagram ..................................................................................................		4
2	Memory Organization ......................................................................................................................			5
	2.1	Programmer’s Models and Memory Maps .............................................................................		5
	2.2	Data Memory (DATA, IDATA, and EDATA).......................................................................		6
		2.2.1	Registers R0 - R7 .....................................................................................................	6
		2.2.2	Bit Addressable RAM ..............................................................................................	7
		2.2.3 Extended Data Memory (EDATA)..........................................................................		7
		2.2.4	Stack .........................................................................................................................	7
		2.2.5	General Purpose RAM ...........................................................................................	10
	2.3	Special Function Registers (SFRs) .......................................................................................		11
	2.4	External Data Memory (XDATA) ........................................................................................		12
	2.5	High Data Memory (HDATA) .............................................................................................		12
	2.6	Program Memory (CODE) ...................................................................................................		14
	2.7	Universal Pointers.................................................................................................................		15
3	51MX Instructions ..........................................................................................................................			20
	3.1	Instruction Set Summary ......................................................................................................		22
	3.2	51MX Operation Code Charts ..............................................................................................		23
4	External Bus		....................................................................................................................................	28
	4.1	Multiplexed .....................................................................................................External Bus		28
5	Interrupt Processing .......................................................................................................................			30
6 P87C51Mx2 Ports, ....................................................................Power Control and Peripherals				34
	6.1	Special ....................................................................................................Function Registers		34
	6.2	P87C51Mx2 .................................................................................................................Ports		37
		6.2.1 ........................................................................................................Ports 0, 1, 2, 3		37
		6.2.2 ......................................................................................................................	Port 4	37
	6.3	P87C51Mx2 ...........................................................................................Low Power Modes		38
		6.3.1 ...................................................................................................	Stop Clock Mode	38
		6.3.2 ...............................................................................................................	Idle Mode	38
		6.3.3 ................................................................................................	Power - Down Mode	38
		6.3.4 .......................................................................................................	Power - On Flag	40
		6.3.5 .............................................................................................	Design Consideration	40
		6.3.6 ......................................................................................................	ONCE™ Mode	40
		6.3.7 ..................................................................	Low Power Eprom Operation (LPEP)	40
	6.4	Timers/Counters .......................................................................................................0 and 1		40
		6.4.1 ...................................................................................................................	Mode 0	41
		6.4.2 ...................................................................................................................	Mode 1	41

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	6.4.3	Mode 2 ...................................................................................................................	41
	6.4.4	Mode 3 ...................................................................................................................	42
6.5	Timer 2	..................................................................................................................................	44
	6.5.1 ........................................................................................................	Capture Mode	44
	6.5.2 ...........................................................	Auto - Reload Mode (Up or Down Counter)	44
	6.5.3 ......................................................................................	Programmable Clock - Out	45
	6.5.4 ......................................	Baud Rate Generator Mode For UART 0 (Serial Port 0)	47
	6.5.5 ........................................................................	Summary Of Baud Rate Equations	48
	6.5.6 .........................................................................................	Timer/Counter 2 Set - up	48
6.6	UARTs ..................................................................................................................................		51
	6.6.1 ...................................................................................................................	Mode 0	51
	6.6.2 ...................................................................................................................	Mode 1	51
	6.6.3 ...................................................................................................................	Mode 2	51
	6.6.4 ...................................................................................................................	Mode 3	51
	6.6.5 .............................................................................	SFR and Extended SFR Spaces	51
	6.6.6 .......................................................................	Baud Rate Generator and Selection	52
	6.6.7 ........................................................................................................	Framing Error	55
	6.6.8 .......................................................................................................	Status Register	56
	6.6.9 ...................................................................................	More About UART Mode 1	57
	6.6.10 .......................................................................	More About UART Modes 2 and 3	58
	6.6.11 ...................................................................................................	Double Buffering	60
	6.6.12 ...........................................................................	Multiprocessor Communications	62
	6.6.13 ............................................................................	Automatic Address Recognition	62
6.7	Watchdog ...................................................................................................................Timer		63
	6.7.1 ................................................................................................	Watchdog Function	63
	6.7.2 .......................................................................................................	Feed Sequence	63
	6.7.3 .........................................................................................................	WDT Control	66
	6.7.4 .........................................................................................	WatchDog Reset Width	66
	6.7.5 ...........................................................................	Reading from the WDCON SFR	66
	6.7.6 ..........................................	Software Reset Via WatchDog Timer Feed Sequence	66
6.8	Additional ...............................................................................................................Features		67
	6.8.1 ..........................................................................	Expanded Data RAM Addressing	67
	6.8.2 .................................................................................................	Dual Data Pointers	68
6.9	Programmable ...................................................................................Counter Array (PCA)		68
	6.9.1 ................................................................................................	PCA Capture Mode	72
	6.9.2 .................................................................................	16 - bit Software Timer Mode	73
	6.9.3 ......................................................................................	High Speed Output Mode	73
	6.9.4 ................................................................................	Pulse Width Modulator Mode	73
	6.9.5 ...........................................................................................	PCA Watchdog Timer	73

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1 INTRODUCTION

1.1THE 51MX CPU CORE

Philips Semiconductor’s 51MX (Memory eXtension) core is based on an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear, unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes (KB) limit to support up to 8 megabytes (MB) of program memory and 8 MB of data memory. It retains full program code compatibility to enable design engineers to reuse 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application-Specific Integrated Circuits (ASICs). However, by entering the Extended Addressing Mode in order to access either data or code beyond 64 KB, the bus interface changes.

The 51MX core is completely backward compatible with the 80C51: code written for the 80C51 may be run on 51MX-based derivatives with no changes.

Summary of differences between the classic 80C51 architecture and the 51MX core:

•Program Counter: The Program Counter is extended to 23 bits.

•Extended Data Pointer: A 23-bit Extended Data Pointer called the EPTR has been added in order to allow simple adjustment to existing assembly language programs that must be expanded to address more than 64 KB of data memory.

•Stack: Two independent alternate Stack modes are added. The first causes addresses pushed onto the Stack by interrupts to be expanded to 23 bits. The second allows Stack extension into a larger memory space.

•Instruction set: A small number of instructions have extended addressing modes to allow full use of extended code and data addressing.

•Addressing Modes: A new addressing mode, Universal Pointer mode, is added that allows accessing all of the data and code areas except for SFRs using a single instruction. This mode produces major improvements in size and performance of compiled programs.

•Six clock cycles per machine cycle.

The 51MX core is described in more details in the 51MX Architecture Reference.

1.2P87C51MX2 MICROCONTROLLERS

The P87C51Mx2 represents the first microcontroller based on the 51MX core. The P87C51MC2 features 96 KB of OTP program memory and 3 KB of data SRAM, while the P87C51MB2 has 64 KB of OTP and 2 KB of RAM. In addition, both devices are equipped with a Programmable Counter Array, a watchdog timer that can be configured to different time ranges, as well as two enhanced UARTs.

The P87C51Mx2 provides greater functionality, increased performance, and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for software workarounds. The increased program memory enables design engineers to develop more complex programs in a highlevel language like C, for example, without struggling to contain the program within the traditional 64 KB of program memory.

These enhancements also greatly improve C language efficiency for code sizes below 64 KB.

KEY FEATURES

•23-bit program memory space and 23-bit data memory space

•96 KB or 64 KB of on-chip OTP

•3 KB or 2 KB of on-chip RAM

•Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

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•Programmable Counter Array (PCA)

•Two full-duplex enhanced UARTs

KEY BENEFITS

•Increases program/data address range to 8 MB each

•Enhances performance and efficiency for C programs

•Fully 80C51-compatible microcontroller

•Provides seamless and compelling upgrade path from classic 80C51

•Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs

•Supported by 80C51 development and programming tools

•The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market

COMPLETE FEATURES

•Fully static

•Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

•96 KB or 64 KB of on-chip OTP

•3 KB or 2 KB of on-chip RAM

•23-bit program memory space and 23-bit data memory space

•Four interrupt priority levels

•32 I/O lines (4 ports)

•Three Timers: Timer0, Timer1 and Timer2

•Two full-duplex enhanced UARTs with baud rate generator

•Framing error detection

•Automatic address recognition

•Power control modes

•Clock can be stopped and resumed

•Idle mode

•Power down mode

•Second DPTR register

•Asynchronous port reset

•Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules

•Low EMI (inhibit ALE)

•Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)

80C51 COMPATIBILITY FEATURES OF THE 51MX CORE

•100% binary compatibility with the classic 80C51 so that existing code is completely reusable

•Linear program and data address range expanded to support up to 8 MB each

•Program counter and data pointers expanded to 23 bits

•Stack pointer extended to 16 bits

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1.3P87C51MX2 LOGIC SYMBOL

VDD VSS

Address Bus 0-7

Data Bus

PORT0

PORT1

RXD0

TXD0

INT0

PORT3

P87C51Mx2

PORT2

INT1

T0

T1

WR

RD

RXD1

TXD1

RST

XTAL2

EA/Vpp

XTAL1

PSEN

ALE/PROG

Figure 1: P87C51Mx2 Logic Symbol

P87C51Mx2 User Manual

P87C51Mx2

T2

T2EX

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

Address Bus 8-15				Address Bus 16-22

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1.4P87C51MX2 BLOCK DIAGRAM

High Performance

80C51 CPU

(51MX Core)

96KB / 64KB									UART 0
Code OTP	Internal Bus
3KB / 2KB									Baud Rate
Data RAM									Generator

UART 1

Port 3

Port 2	Timer0
	Timer1

Port 1	Watchdog Timer

Port 0	PCA
	(Programmable
	Counter Array)

	Crystal or	Oscillator	Timer2
	Resonator

Figure 2: P87C51Mx2 Block Diagram

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2 MEMORY ORGANIZATION

2.1PROGRAMMER’S MODELS AND MEMORY MAPS

The P87C51Mx2 retains all of the 80C51 memory spaces. Additional memory space has been added transparently as part of the means for allowing extended addressing. The basic memory spaces include code memory (which may be on-chip, off-chip, or both); external data memory; Special Function Registers; and internal data memory, which includes on-chip RAM, registers, and stack. Provision is made for internal data memory to be extended, allowing a larger processor stack.

The P87C51Mx2 programmer’s model and memory map is shown in Figure 3.

CODE

On-Chip and/or Off-Chip Code Memory

8 MB Code

Memory Space

7F:FFFFh

Two 24-bit Universal Pointers

R7

R6

R5

R3

R2

R1

23-bit Program Counter

23-bit Extended Data Pointer

Two 16-bit DPTRs

16-bit Stack Pointer

PSW

B

A

EDATA

(includes DATA & IDATA)

Extended Data

Memory

(stack and indirect

addressing)

Extended SFRs

IDATA

(includes DATA)

Special Function

256 Byte On-Chip

Registers

Data Memory

(directly addressable)

(stack and indirect

addressing)

DATA

128 Byte On-Chip

Data Memory

(stack, direct and indirect

addressing)

Four Register Banks

00:0000h

R0 - R7

Data Memory Space

(DATA, IDATA, EDATA)

4FFh

100h FFh

80h

7Fh

00h

7E:FFFFh

HDATA

(includes XDATA)

Off-Chip

Data Memory

00:07FFh XDATA 00:06FFh

1792 Bytes On-Chip

Data Memory

(P87C51MC2)

00:0300h XDATA 00:02FFh

768 Bytes On-Chip

Data Memory

(P87C51MB2)

00:0000h

8 MB - 64 KB External

Data Memory Space

(XDATA, HDATA)

Figure 3: P87C51MB2/C2 Programmer’s Model and Memory Map

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Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary.

DATA	128 bytes of internal data memory space (00h...7Fh) accessed via direct or indirect addressing, using instructions
	other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA	Indirect Data. 256 bytes of internal data memory space (00h...FFh) accessed via indirect addressing using
	instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA
	area and the 128 bytes immediately above it.
EDATA	Extended Data. This is a superset of DATA and IDATA areas. Both P87C51MB2 and P87C51MC2 have 1280 bytes
	of SRAM in EDATA memory. The added area may be accessed only as Stack and via indirect addressing using
	Universal Pointers. The Stack may reside in the extended area if enabled to do so.
SFR	Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via
	direct addressing (addresses in range 80h...FFh). This includes the new 51MX extended SFRs.
XDATA	"External" Data. Duplicates the classic 80C51 64 KB memory space addressed via the MOVX instruction using the
	DPTR, R0, or R1. On-chip XDATA can be disabled under program control. Also, XDATA may be placed in external
	devices. P87C51MB2 has 768 bytes of on-chip XDATA memory space and P87C51MC2 has 1792 bytes of on-chip
	XDATA memory space.
HDATA	"High" Data. This is a superset of XDATA and may include up to 8,323,072 bytes (8 MB - 64 KB) of memory space
	addressed via the MOVX instruction using the EPTR, DPTR, R0, or R1. Non XDATA portion of HDATA is placed in
	external devices.
CODE	Up to 8 MB of Code memory, accessed as part of program execution and via the MOVC instruction.

All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV instruction. This feature is detailed in a subsequent section.

2.2DATA MEMORY (DATA, IDATA, AND EDATA)

The standard 80C51 internal data memory consists of 256 bytes of DATA/IDATA RAM, and is always entirely on-chip. In this space are the data registers R0 through R7, the default stack, a bit addressable RAM area, and general purpose data RAM. On the top of the DATA/IDATA memory space is a 1 KB block of RAM that can be accessed as stack or via indirect addressing. Alltogether this forms EDATA RAM of 1280 bytes. The different portions of the data memory are accessed in different manners as described in the following sections.

2.2.1REGISTERS R0 - R7

General purpose registers R0 through R7 allow quick, efficient access to a small number of internal data memory locations. For example, the instruction:

MOV A,R0

uses one byte of code and executes in one machine cycle. Using direct addressing to accomplish the same result as in:

MOV A,10h

requires two bytes of code memory and executes in two machine cycles. Indirect addressing further requires setup of the pointer register, etc.

These registers are “banked”. There are four groups of registers, any one of which may be selected to represent R0 through R7 at any particular time. This feature may be used to minimize the time required for context switching during an interrupt service or a subroutine, or to provide more register space for complicated algorithms.

The registers are no different from other internal data memory locations except that they can be addressed in "shorthand" notation as "R0", "R1", etc. Instructions addressing the internal data memory by other means, such as direct or indirect addressing, are quite capable of accessing the same physical locations as the registers in any of the four banks.

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2.2.2BIT ADDRESSABLE RAM

Internal data memory locations 20 hex through 2F hex may be accessed as both bytes and bits. This allows a convenient and efficient way to manipulate individual flag bits without using much memory space. The bottom bit of the byte at address 20h is bit number 00h, the next bit in the same byte is bit number 01h, etc. The final bit, bit 7 of the byte at address 2Fh, is bit number 7Fh (127 decimal). Bit numbers above this refer to bits in Special Function Registers.

This code:
SETB	20h.1
CPL	20h.2
JNB	20h.2, LABEL1

sets bit 1 at address 20 hex, complements bit 2 in the same byte, then branches if the second bit is not equal to 1. In an actual program, these bits would normally be given names and referred to by those names in the bit manipulation instructions.

2.2.3EXTENDED DATA MEMORY (EDATA)

The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic 80C51s. This space can be used as an extended or alternative processor stack space, or can be used as general purpose storage under program control. Other than Stack Pointer based access to this space, which is automatic if Extended Stack Memory Mode is enabled (see the following Stack section), this memory is addressed only using the new Universal Pointer feature. Universal Pointers are described in a later section.

Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory.

2.2.4STACK

The processor stack provides a means to store interrupt and subroutine return addresses, as well as temporary data. The stack grows upwards, from lower addresses towards higher addresses. The current Stack Pointer always points to the last item pushed on the stack, unless the stack is empty. Prior to a push operation, the Stack Pointer is incremented, then data is written to memory. When the stack is popped, the reverse procedure is used. First, data is read from memory, then the Stack Pointer is decremented.

The default configuration of the 51MX stack is identical to the classic 80C51 stack implementation. When interrupt or subroutine addresses are pushed onto the stack, only the lower 16 bits of the Program Counter are stored. This default 80C51 mode stack operation is shown in Figure 4.

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This figure applies to the ACALL and LCALL instructions in all modes. In 80C51 stack mode, it also applies to interrupt processing.

		0083h
		0082h
				Final SP Value (after ACALL,
	PCH (PC.15-8)	0081h
				LCALL or Interrupt)
	PCL (PC.7-0)	0080h
		007Fh		Initial SP Value (before
				ACALL, LCALL, or interrupt)

Figure 4: Return Address Storage on the Stack (80C51 Mode)

There are two configuration options for the stack. For purposes of backward compatibility with the classic 80C51, both alternate modes are disabled by a chip reset. The first option, Extended Interrupt Frame Mode, causes interrupts to push the entire 23-bit Program Counter onto the stack (as three bytes), and the RETI instruction to pop all 23-bits as a return address, as shown in Figure 5. The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a "1" to be consistent with Universal Pointer addressing.

Storing the full 23-bit Program Counter value is a requirement for systems that include more than 64 KB of program, since an interrupt could occur at any point in the program. The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruction only, while other calls and returns are not affected. Special extended call and return instructions allow large programs to traverse the entire code space with full 23-bit return addresses. The Extended Interrupt Frame Mode is enabled by setting the EIFM bit in the MXCON register.

This figure applies to interrupt services in Extended Interrupt Frame Mode, as well as the ECALL instruction in all modes.

The upper bit of the byte containing PCE is forced to a "1" in order to be consistent with Universal Pointers.

		0083h
	PCE (PC.22-16)	0082h		Final SP Value (after
				ECALL or interrupt)
	PCH (PC.15-8)	0081h
	PCL (PC.7-0)	0080h
		007Fh		Initial SP Value (before
				ECALL or interrupt)

Figure 5: Extended Return Address Storage on the Stack

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The second stack option, Extended Stack Memory Mode, allows for stack extension beyond the 256 byte limit of the classic 80C51 family. Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory. Stack extension has no effect on the data that is stored on the stack, it will continue to be stored as shown on in figures 4 and 5. The Extended Stack Memory Mode is enabled by setting the ESMM bit in the MXCON register.

If the Stack Pointer is not initialized by software, the stack will begin at on-chip RAM address 8, just as for the 80C51. Also note that in Extended Stack Memory Mode, both MB2 and MC2 parts have 1KB of RAM on the top of DATA/IDATA space available for the stack.

The stack mode bits ESMM and EIFM are shown in Figure 6. Note that the stack mode bits are intended to be set once during program initialization and not altered after that point. Changing stack modes dynamically may cause stack synchronization problems.

MXCON Address: FFh (51MX Extended SFR Space)
Not bit addressable		7		6	5	4	3		2	1	0
Reset Value: 00h			-	-	-	-	-		EAM	ESMM	EIFM
BIT	SYMBOL	FUNCTION
MXCON.7 - 3	-	Reserved. Programs should not write a 1 to these bits.
MXCON.2	EAM	Enables Extended Addressing Mode, in connection with a non-volatile user configuration
		bit. The logical OR of the SFR bit and the non-volatile configuration bit determines whether
		code and data addressing beyond 64 KB is allowed. The same logical OR value will be

read from this bit by software. When 0, all addressing (on-chip and off-chip) is limited to 64 KB each of code and data. When 1, 51MX addressing capabilities are extended beyond boundary of 64 KB to 8 MB each of code and data, and upper address bits are multiplexed on Port 2 for external code and/or data accesses. Refer to the External Bus section for additional details.

EAM must be set to EAM=1 if at least one of the next two statements is true:

		- there is executable code or constants in CODE space are above 64 KB
		- address of data byte that has to be accessed in HDATA is above 64 KB
MXCON.1	ESMM	Enables the Extended Stack Memory Mode. When ESMM = 0, the Stack Pointer is 8 bits
		in width and the stack is located in the IDATA memory space. When ESMM = 1, the Stack
		Pointer is increased to 16-bits in width and the stack may be located anywhere in the
		EDATA space. ESMM is independent of EAM and EIFM bits.
MXCON.0	EIFM	Enables the Extended Interrupt Frame Mode. When EIFM = 0, an interrupt service will
		cause only the lower 16 bits of the PC to be pushed onto the stack, and an RETI
		instruction will restore only the lower 16 bits of the PC. When EIFM = 1, an interrupt
		service will cause all 23 bits of the PC to be pushed onto the stack, while an RETI
		instruction will restore all 23 bits of the PC. EIFM must be set to one if the application
		allows execution beyond the first 64 KB of code memory.
		Figure 6: MX Configuration Register (MXCON)

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2.2.5GENERAL PURPOSE RAM

Portions of the internal data memory that are not used in a particular application as registers, stack, or bit addressable locations may be considered general purpose RAM and used in any desired manner.

The lower 128 bytes of the internal data memory (DATA) may be accessed using either direct or indirect addressing. Direct addressing incorporates the entire address within the instruction. For example, the instruction:

MOV 31h,#10

will store the value 10 (decimal) in location 31 hex. Direct addresses above 128 will access the Special Function Registers rather than the internal data memory.

Indirect addressing takes an address from either R0 or R1 of the current register bank and uses it to identify a location in the internal data memory. The entire 256 byte internal data memory space (IDATA) may be accessed using indirect addressing. For example, the instruction sequence:

MOV	R0,#90h
MOV	A,@R0

will cause the contents of location 90 hex to be loaded into the accumulator. It is typical with the classic 80C51 to cause the stack to be located in the upper area, leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect addressing. With the 51MX, the stack may be extended and moved completely out of the lower 256 bytes of memory.

			8 Bytes
7F						78
77						70
6F						68
67						60	Undedicated
5F						58
							Area
57						50
4F						48
47						40
3F						38
37						30
2F	bit 7F …					28	Bit Addressable
27				… bit 0		20	Segment
1F			bank 3			18
17			bank 2			10	Register
0F			bank 1			08	Banks
07			bank 0			00

Figure 7: Internal Data Memory, Lower 128 Bytes

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2.3SPECIAL FUNCTION REGISTERS (SFRS)

Special Function Registers (SFRs) provide a means for the processor to access internal control registers, peripheral devices, and I/O ports. An SFR address is always contained entirely within an instruction.

The standard SFR space is 128 bytes in size. SFRs are implemented in each 51MX device as needed in order to provide control for peripherals or access to CPU features and functions. Undefined SFRs are considered "reserved" and should not be accessed by user programs.

Sixteen addresses in the SFR space are both byteand bit-addressable. The bit-addressable SFRs are those whose address ends in 0h or 8h (i.e. 80h, 88h, ..., F8h). Bit addressing allows direct control and testing of bits in those SFRs.

All 51MX devices also have additional 128 bytes of extended SFRs as discussed in the "51MX Architecture Reference". Figures 8 and 9 show the SFR and the Extended SFR maps for P87C51MB2/C2 parts.

	0 / 8	1 / 9	2 / A	3 / B	4 / C	5 / D	6 / E	7 / F
									FF
F8	IP1	CH	CCAP0H	CCAP1H	CCAP2H	CCAP3H	CCAP4H
F0	B							IP1H	F7
E8	IEN1	CL	CCAP0L	CCAP1L	CCAP2L	CCAP3L	CCAP4L		EF
E0	ACC								E7
D8	CCON	CMOD	CCAPM0	CCAPM1	CCAPM2	CCAPM3	CCAPM4		DF
D0	PSW								D7
C8	T2CON	T2MOD	R2CAPL	R2CAPH	TL2	TH2			CF
C0									C7
B8									BF
	IP0	S0ADEN
B0	P3							IP0H	B7
A8	IEN0	S0ADDR							AF
A0	P2		AUXR1				WDRST		A7
98	S0CON	S0BUF							9F
90	P1								97
88	TCON	TMOD	TL0	TL1	TH0	TH1	AUXR		8F
80	P0	SP	DPL	DPH				PCON	87
	↑
Bit Addressable SFRs

Figure 8: Standard SFR Map for the P87C51Mx2

Figure 9 shows the extended SFR map for the P87C51Mx2.

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	0 / 8		1 / 9	2 / A	3 / B	4 / C	5 / D	6 / E	7 / F
F8										FF
					SPE	EPL	EPM	EPH	MXCON
F0										F7
E8										EF
E0										E7
D8										DF
D0										D7
C8										CF
C0										C7
B8										BF
B0										B7
A8										AF
A0										A7
98										9F
90										97
88										8F
						S0STAT			WDCON
80		S1CON	S1BUF	S1ADDR	S1ADEN	S1STAT	BRGCON	BRGR0	BRGR1	87
		↑
	Bit Addressable SFRs

Figure 9: Extended SFRs Map for the P87C51Mx2

2.4EXTERNAL DATA MEMORY (XDATA)

The XDATA space on the 51MX is the same as the 64 KB external data memory space on the classic 80C51.

On-chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register. Accesses above implemented on-chip XDATA will be routed to the external bus. If on-chip XDATA memory is disabled, all XDATA accesses will be routed to the external bus. P87C51MB2 has 768 bytes of on-chip XDATA, while P87C51MC2 has 1792 bytes of on-chip XDATA memory.

2.5HIGH DATA MEMORY (HDATA)

The 51MX architecture supports up to an 8 MB data memory space, using 23-bit addressing. The entire 8 megabyte space except for the 64 KB EDATA space is called HDATA. The XDATA space comprises the lower 64 KB of HDATA.

Data Pointers

The 51MX adds an additional 23-bit Extended Data Pointer (EPTR) in order to allow a simple method of extending existing 80C51 programs to use more than 64 KB of data memory. If we want to access a single data byte from HDATA RAM located above the first 64 KB, EAM bit in MXCON sfr must be set to EAM=1.

All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR. The 23-bit EPTR is comprised of (in order) EPH, EPM, and EPL. Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR respectively. Since the EPTR is a 23-bit value, the 8th bit of EPH is not used. If read, it will return a 1, like other unimplemented bits in SFRs. Use of the EPTR allows access to the entire HDATA space, including XDATA.

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At any point in time, one specific Data Pointer is active and is used by instructions that reference the DPTR. The active DPTR may be changed by altering the Data Pointer Select (DPS) bit. The DPS bit occupies the bottom bit of the AUXR1 register. The DPS bit applies only to the two DPTRs, not to the EPTR.

In the indirect addressing mode, the currently active DPTR or the EPTR provides a data memory address for accessing the XDATA and HDATA space respectively. When the DPTR is used for addressing, only the XDATA space is available. When the EPTR is used for addressing, the entire HDATA space (which includes the XDATA space) may be accessed. If the EPTR value exceeds 7E:FFFF (the limit of HDATA), data accesses using EPTR will yield undefined results. The reason for limiting HDATA addresses is to keep the addressing uniform for EPTR addressing and Universal Pointer addressing (which is explained in a later section of this document).

Example Instruction:	External Data
MOVX @DPTR,A	Memory

DPS

Data Pointers

(00:A17Ch)

Location

0

= A17Ch

00:A17Ch:

Accumulator

0

1

= 2962h

33h

33h

Figure 10: External Data Memory Access using Indirect Addressing with DPTR

Example Instruction:					External Data
MOVX A,@EPTR					Memory
	EPTR				Location
					01:1034h:			Accumulator
	0 = 01:1034h
					3Bh			3Bh

Figure 11: External Data Memory Access using Indirect Addressing with EPTR

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2.6PROGRAM MEMORY (CODE)

The 80C51, and thus the 51MX, are "Harvard" architectures, meaning that the code and data spaces are separated. If there is a single byte of executable code above 64 KB, EAM bit in MXCON sfr must be set to EAM=1. Also, if there is constant in CODE space above 64 KB boundary that is read by the application, EAM must be set to EAM=1, too.

The 51MX expands the 80C51 Program Counter to 23 bits, providing a contiguous, unsegmented linear code space that may be as large as 8 MB. On-chip space begins at code address 0 and extends to the limit of the on-chip code memory. Above that, code will be fetched from off-chip. The 51MX architecture allows for an external bus which supports:

•Mixed mode (some code and/or data memory off-chip).

•Single-chip operation (no external bus connection).

•ROMless operation (no use of on-chip code memory).

In some cases, code memory may be addressed as data. Extended instruction address modes provide access to the entire code space of 8 MB through the use of indexed indirect addressing. The currently active DPTR, the EPTR, a Universal Pointer, or the Program Counter may be used as the base address. Examples of the various code memory addressing modes are shown in figures 12 through 14.

Following a reset, the 51MX begins code execution like a classic 80C51, at address 00:0000h. Similarly, the interrupt vectors are placed just above the reset address, starting at address 00:0003h. It is important to note that first instruction (located at address 0) should not be an EJMP instruction. EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt 0 vector address.

Example Instruction:

Code

MOVC A,@A+PC

Memory

Accumulator

D3h

PC

Location

3E:97FFh

+

(3E:98D2h)

3E:98D2h:

Accumulator

70h

70h

Figure 12: Code Memory Access using Indexed Indirect Addressing with the Program Counter

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Example Instruction:						Code
MOVC	A,@A+DPTR					Memory
executed at address 01:59B3					Upper 7 bits of
			Accumulator
			A2h		Program Counter
		Data Pointers			(01h)
DPS						Location
		0 = C340h		(FFAEh)		01:FFAEh:	Accumulator
1			+
		1 = FF0Ch				C1h	C1h
					01:FFAEh

Figure 13: Code Memory Access using Indexed Indirect Addressing with DPTR

Example Instruction:

Code

MOVC A,@A+EPTR

Memory

Accumulator

CDh

EPTR

Location

12:B109h

+

(12:B1D6h)

12:B1D6h:

Accumulator

55h

55h

Figure 14: Code Memory Access using Indexed Indirect Addressing with EPTR

2.7UNIVERSAL POINTERS

A new addressing mode called Universal Pointer mode has been added to the 51MX, specifically for the purpose of greatly enhancing C language code density and performance. This addressing mode allows access to any of the on-chip or off-chip code and data spaces using one instruction, without the need to know in advance which of the different spaces the data will reside in. This includes the DATA, IDATA, EDATA, XDATA, HDATA, and CODE spaces. The SFR space is the only space that may not be accessed using the Universal Pointer mode.

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The Universal Pointer addressing mode uses a new set of pointer registers for two reasons. The first is that 24-bit pointers are needed in order to allow addressing both the 8 MB code space and the 8 MB data space. The other reason is that it is much more efficient to manipulate multi-byte pointer values in registers than it is in SFRs. C compilers typically already perform pointer manipulation in registers, then move the result to a Data Pointer for use.

Two Universal Pointers are supported: PR0 and PR1. The pointer PR0 is composed of registers R1, R2, and R3 of the current register bank, while PR1 is composed of registers R5, R6, and R7 of the current register bank, as shown in Figure 15.

PR0

PR1

MSB		LSB
R3	R2	R1

MSB		LSB
R7	R6	R5

Figure 15: Universal Pointer Registers

In order to access all of the various memory spaces in a single unified manner, they must all be mapped into a new "view" that allows 16 MB of total memory space. This new view is called the Universal Memory Map.

The XDATA space is placed at the bottom of this new address map. The HDATA space continues above XDATA. The standard internal data memory spaces (DATA and IDATA) are above HDATA, followed by the remainder of the EDATA space. Finally, the code memory occupies the top of the map.

Thus, the most significant bit of the Universal Pointer determines whether code or data memory is accessed. By placing the XDATA space at the bottom of the Universal Memory Map, Universal Pointer addresses 00:0000 through 00:FFFF can correspond to the classic 80C51 external data memory space. This allows for full backward compatibility for code that does not need more than 64 KB of external data space. The Universal Memory Map is shown in Figure 16, while the standard view of the memory spaces and how they relate to Universal Pointer values are shown in Figure 17.

The Universal Pointers are used only by a new 51MX instruction called EMOV. The EMOV instruction allows moving data via one of the Universal Pointers into or out of the accumulator. In either case, a displacement of 0, 1, 2, or 3 may also be specified, which is added to the pointer prior to its use. The displacement allows C compiler access of variables of up to 4 bytes in size (e.g. Long Integers) without the need to alter the pointer value. An example of Universal Pointer usage is shown in Figure 18. Note that it is not possible to store a value to the CODE area of the Universal Memory Map.

Another new instruction is added to allow incrementing one of the Universal Pointers by a value from 1 to 4. This allows the pointer to be advanced past the last data element accessed, to the next data element.

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Memory Space

CODE

EDATA

IDATA

HDATA

XDATA

Up to 8 MB on-Chip and/or off-Chip

program memory

Up to 64 KB - 256 bytes on-chip and/or off-chip data accessed as Stack and via Universal Pointer only

Upper 128 bytes on-chip indirectly addressed

RAM

Lower 128 bytes DATA on-chip directly & indirectly

addressed RAM

Up to 8 MB - 128 KB data accessed via MOVX (generally off-chip data)

Up to 64 KB on-chip and/or off-chip

data accessed via MOVX

FF:FFFFh

80:0000h 7F:FFFFh

7F:0100h 7F:00FFh

7F:0080h 7F:007Fh

7F:0000h

7E:FFFFh

01:0000h

00:FFFFh

Addressing Modes

PC, PC relative addressing DPTR (lower 64 KB of Code) EPTR

Universal Pointers: PR0, PR1

Stack (SPE / SP)

Universal Pointers: PR0, PR1

R0, R1

Stack (SPE / SP)

Universal Pointers: PR0, PR1

Direct addressing R0, R1 indirect Stack (SPE / SP)

Universal Pointers: PR0, PR1

R0, R1 (lower 256 bytes on-chip, lower 64 KB off-chip via use of P2)

DPTR (XDATA access only) EPTR (HDATA access) Universal Pointers: PR0, PR1

00:0000h

Figure 16: Universal Memory Map

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16MB

CODE

8MB

DATA,

IDATA,

EDATA

								HDATA
CODE									HDATA,
									XDATA
			EDATA
								XDATA
			IDATA
			DATA						0

Standard Memory Map 24-bit Addressing using PR1 and PR2

Figure 17: Mapping of other Addressing Modes to Universal Pointer Addressing

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Example Instruction:	Universal
EMOV @PR0+1,A	Memory Map

	1
PR0							Location
12:C340h			+ (12:C341h)				12:C341h:			Accumulator
							39h			39h

Figure 18: Memory Access using Universal Pointer Addressing

Universal Pointers are designed primarily to facilitate addressing in Extended Addressing Mode, with the EAM bit in MXCON set to one. However, Universal Pointers may still be used when EAM = 0. In this case, Universal Pointer addressing can access only the bottom 64 KB of the Code space, the 64 KB XDATA space, and the 64 KB EDATA space. The Universal Pointer values that point to these areas do not change. When EAM = 0, Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex.

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3 51MX INSTRUCTIONS

The 51MX instruction set is a a true binary-level superset of the classic 80C51, designed to be fully compatible with previously written 80C51 code. The changes to the instruction set are all related to the expanded address space. Some details of existing instructions have been altered, and some instructions have had an extended mode added. In the latter case, the alternate mode of the instruction is activated by preceding the instruction with a special one-byte prefix code, A5h.

An important goal in the implementation of the 51MX was to keep the same timing relationship of existing 80C51 instructions to existing devices. Any 80C51 instruction executed on the 51MX will take the same number of machine cycles to execute.

	80C51 Instruction		Effect of Extended Addressing
	All relative branches		Includes SJMP and all conditional branches. These instructions may cross a 64 KB boundary if they
			are located within branch range of the boundary.
	ACALL	addr11	This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence
			is across the boundary.
	AJMP	addr11	This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence
			is across the boundary.
			The lower 16-bits of the Program Counter are replaced with the value formed by the sum of the
	JMP	@A+DPTR	Accumulator and the active DPTR. This instruction will cross a 64 KB boundary if it is located such
			that the next instruction in sequence is across the boundary.
			The address formed by replacing the lower 16-bits of the Program Counter with the value formed
	MOVC	A,@A+DPTR	by the sum of the Accumulator and the active DPTR is used to access code memory. The PC value
			used is that of the instruction following MOVC.
	MOVC	A,@A+PC	The sum of the Accumulator and the 23-bit Program Counter forms the 23-bit address used to read
			the code memory. The PC value used is that of the instruction following MOVC.
	MOVX	@DPTR,A	The active DPTR points to an address in the 64 KB XDATA memory.
	MOVX	A,@DPTR	The active DPTR points to an address in the 64 KB XDATA memory.
			Replaces the lower 16 bits of the Program Counter with a 16-bit address from the Stack. This
	RET		instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is
			across the boundary.
			When the extended interrupt frame mode is not enabled, this instruction replaces the lower 16 bits
			of the Program Counter with a 16-bit address from the Stack. This will cause a 64 KB boundary to
	RETI		be crossed if the instruction is located such that the next instruction in sequence is across the
			boundary. If the extended interrupt frame mode is enabled, a 23-bit address is loaded into the PC
			from the stack.
	LCALL	addr16	Replaces the lower 16 bits of the Program Counter with the 16-bit address. This instruction will cross
			a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.
	LJMP	addr16	Replaces the lower 16 bits of the Program Counter with the 16-bit address. This instruction will cross
			a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.
			Table 1: Instructions Affected by Extended Address Space

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80C51 Instruction		51MX Effect		51MX Enhancement		51MX Effect with Prefix
				(these instructions use
		Without Prefix
				the prefix byte)
LCALL	addr16	Load a 16-bit address into the		ECALL addr23		Load a 23-bit address into the Program
		Program Counter.				Counter.
LJMP	addr16	Load a 16-bit address into the		EJMP	addr23	Load a 23-bit address into the Program
		Program Counter.				Counter.
		The lower 16-bits of the
		Program Counter are replaced				The Program Counter is loaded with the
JMP	@A+DPTR	with the sum of the		JMP	@A+EPTR	value formed by the sum of the Accumulator
		Accumulator and the active				and the EPTR.
		DPTR.
		Code memory is accessed
		using the address formed by				Code memory is accessed using the
MOVC	A,@A+DPTR	replacing the lower 16-bits of
				MOVC A,@A+EPTR		address formed by the sum of the
		the Program Counter with the
		sum of the Accumulator and				Accumulator and the EPTR.
		the active DPTR.
		The active DPTR points to an				The EPTR points to an address anywhere in
MOVX	@DPTR,A	address in the 64 KB XDATA		MOVX @EPTR,A		HDATA memory (not DATA, IDATA, or
		memory.				EDATA).
		The active DPTR points to an				The EPTR points to an address anywhere in
MOVX	A,@DPTR	address in the 64 KB XDATA		MOVX A,@EPTR		HDATA memory (not DATA, IDATA, or
		memory.				EDATA).
INC	DPTR	Increment the active Data		INC	EPTR	Increment the 23 bit EPTR.
		Pointer.
MOV	DPTR,#data16	Load a 16-bit value into the		MOV	EPTR,#data23	Load a 23-bit value into the EPTR.
		active Data Pointer.
		Load a 16-bit address into the				Load a 23-bit address into the Program
RET		Program Counter from the		ERET
						Counter from the Stack.
		Stack.
						Load the Accumulator with the value from
ORL	A,Rn	Logically OR Register n to the		EMOV A,@PRi+disp		the Universal Memory Map at the address
		Accumulator.				formed by PR0 or PR1plus the
						displacement (a value from 0 to 3).
						Load the Universal Memory Map address
ANL	A,Rn	Logically AND Register n to the		EMOV @PRi+disp,A		formed by PR0 or PR1 plus the
		Accumulator.				displacement (a value from 0 to 3) with the
						contents of the Accumulator.
		Exclusive OR Register n to the				Add an immediate data value from 1 to 4 to
XRL	A,Rn			ADD	PRi,#data2	the specified Universal Pointer. This is a 24-
		Accumulator.				bit addition.
	Table 2: Enhancements to the 80C51 Instruction Set Enabled by the Prefix Byte

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