Philips P87C51MB2, P87C51MC2 Technical data

INTEGRATED CIRCUITS

USER’S MANUAL

P87C51MB2/P87C51MC2

80C51 8-bit microcontroller family with extended me mory

64KB/96KB OTP with 2KB/3KB RAM

Preliminary 2002 June 28

Version 0.95

Philips Semiconductors

Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

1 INTRODUCTION ............................................................................................................................1

1.1 The 51MX CPU CORE ..........................................................................................................1

1.2 P87C51Mx2 microcontrollers.................................................................................................1

1.3 P87C51Mx2 Logic Symbol....................................................................................................3

1.4 P87C51Mx2 Block Diagram ..................................................................................................4

2 Memory Organization......................................................................................................................5

2.1 Programmer’s Models and Memory Maps.............................................................................5

2.2 Data Memory (DATA, IDATA, and EDATA).......................................................................6

2.2.1 Registers R0 - R7.....................................................................................................6

2.2.2 Bit Addressable RAM..............................................................................................7

2.2.3 Extended Data Memory (EDATA)..........................................................................7

2.2.4 Stack.........................................................................................................................7

2.2.5 General Purpose RAM...........................................................................................10

2.3 Special Function Registers (SFRs).......................................................................................11

2.4 External Data Memory (XDATA)........................................................................................12

2.5 High Data Memory (HDATA) .............................................................................................12

2.6 Program Memory (CODE) ...................................................................................................14

2.7 Universal Pointers.................................................................................................................15

3 51MX Instructions..........................................................................................................................20

3.1 Instruction Set Summary ......................................................................................................22

3.2 51MX Operation Code Charts..............................................................................................23

4 External Bus....................................................................................................................................28

4.1 Multiplexed External Bus.....................................................................................................28

5 Interrupt Processing.......................................................................................................................30

6 P87C51Mx2 Ports, Power Control and Peripherals....................................................................34

6.1 Special Function Registers....................................................................................................34

6.2 P87C51Mx2 Ports.................................................................................................................37

6.2.1 Ports 0, 1, 2, 3 ........................................................................................................37

6.2.2 Port 4......................................................................................................................37

6.3 P87C51Mx2 Low Power Modes...........................................................................................38

6.3.1 Stop Clock Mode ...................................................................................................38

6.3.2 Idle Mode...............................................................................................................38

6.3.3 Power-Down Mode................................................................................................38

6.3.4 Power-On Flag.......................................................................................................40

6.3.5 Design Consideration.............................................................................................40

6.3.6 ONCE™ Mode ......................................................................................................40

6.3.7 Low Power Eprom Operation (LPEP)..................................................................40

6.4 Timers/Counters 0 and 1.......................................................................................................40

6.4.1 Mode 0...................................................................................................................41

6.4.2 Mode 1...................................................................................................................41

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6.4.3 Mode 2...................................................................................................................41

6.4.4 Mode 3...................................................................................................................42

6.5 Timer 2..................................................................................................................................44

6.5.1 Capture Mode ........................................................................................................44

6.5.2 Auto-Reload Mode (Up or Down Counter)...........................................................44

6.5.3 Programmable Clock-Out......................................................................................45

6.5.4 Baud Rate Generator Mode For UART 0 (Serial Port 0) ......................................47

6.5.5 Summary Of Baud Rate Equations........................................................................48

6.5.6 Timer/Counter 2 Set-up .........................................................................................48

6.6 UARTs..................................................................................................................................51

6.6.1 Mode 0...................................................................................................................51

6.6.2 Mode 1...................................................................................................................51

6.6.3 Mode 2...................................................................................................................51

6.6.4 Mode 3...................................................................................................................51

6.6.5 SFR and Extended SFR Spaces .............................................................................51

6.6.6 Baud Rate Generator and Selection.......................................................................52

6.6.7 Framing Error ........................................................................................................55

6.6.8 Status Register .......................................................................................................56

6.6.9 More About UART Mode 1...................................................................................57

6.6.10 More About UART Modes 2 and 3 .......................................................................58

6.6.11 Double Buffering...................................................................................................60

6.6.12 Multiprocessor Communications...........................................................................62

6.6.13 Automatic Address Recognition............................................................................62

6.7 Watchdog Timer ...................................................................................................................63

6.7.1 Watchdog Function................................................................................................63

6.7.2 Feed Sequence .......................................................................................................63

6.7.3 WDT Control.........................................................................................................66

6.7.4 WatchDog Reset Width .........................................................................................66

6.7.5 Reading from the WDCON SFR ...........................................................................66

6.7.6 Software Reset Via WatchDog Timer Feed Sequence ..........................................66

6.8 Additional Features...............................................................................................................67

6.8.1 Expanded Data RAM Addressing..........................................................................67

6.8.2 Dual Data Pointers.................................................................................................68

6.9 Programmable Counter Array (PCA) ...................................................................................68

6.9.1 PCA Capture Mode................................................................................................72

6.9.2 16-bit Software Timer Mode .................................................................................73

6.9.3 High Speed Output Mode ......................................................................................73

6.9.4 Pulse Width Modulator Mode................................................................................73

6.9.5 PCA Watchdog Timer ...........................................................................................73

2 Preliminary 2002 June 28

Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

1 INTRODUCTION

1.1 THE 51MX CPU CORE

Philips Semiconductor’s 51MX (Memory eXtension) core is based on an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear, unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes (KB) limit to support up to 8 megabytes (MB) of program memory and 8 MB of data memory. It retains full prog ram code compat ibility to enable design engin eers to re use 80C51 develo pment too ls, elim inating the need to move to a new, unfamiliar architecture. The 51MX core retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application-Specific Integrated Circuits (ASICs). However, by entering the Extended Addressing Mode in order to access either data or code beyond 64 KB, the bus interface changes.

The 51MX core is completely backward compatible with the 80C51: code written for the 80C51 may be run on 51MX-based derivatives with no changes.

Summary of differences between the classic 80C51 architecture and the 51MX core:

• Program Counter: The Program Counter is extended to 23 bits.

• Extended Data Pointer: A 23-bit Extended Data Poi nter cal le d th e EPTR h as b ee n ad ded in order to allow simp le a dju stment to existing assembly language programs that must be expanded to address more than 64 KB of data memory.

• Stack: Two independent alte rnate Stack mo des are adde d. The first causes addresses pu shed onto the Stac k by interrupts to be expanded to 23 bits. The second allows Stack extension into a larger memory space.

• Instruction set: A small number of instructions have extended addressing modes to allow full use of extended code and data addressing.

• Addressing Modes: A new addre ssing mo de, Univers al Pointe r mode, is adde d that al lows acc essi ng all of the data and cod e areas except for SFRs using a single instruction. This mode produces major improvements in size and performance of compiled programs.

• Six clock cycles per machine cycle.

The 51MX core is described in more details in the 51MX Architecture Reference.

1.2 P87C51MX2 MICROCONTROLLERS

The P87C51Mx2 represe nts the first micr ocontroller based on the 51MX core. The P87 C51MC2 featur es 96 KB of OTP program memory and 3 KB of data SRAM, while the P87C51MB2 has 64 KB of OTP and 2 KB of RAM. In addition, both devices are equipped with a Programm ab le Counter Array, a watchdog timer that c an be co nfi gure d to d iffe rent time ranges, as well as two enhanced UARTs.

The P87C51Mx2 provide s greater functionality , increased performa nce, and overall lowe r system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for software workarounds. The increased pro gram me mory enable s design eng ineers to develo p more compl ex progra ms in a highlevel language like C, for example, without struggling to contain the program within the traditional 64 KB of program memory. These enhancements also greatly improve C language efficiency for code sizes below 64 KB.

KEY FEATURES

• 23-bit program memory space and 23-bit data memory space

• 96 KB or 64 KB of on-chip OTP

• 3 KB or 2 KB of on-chip RAM

• Up to 24 MHz CPU clock with 6 cloc k cycles per machine cycle

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• Programmable Counter Array (PCA)

• Two full-duplex enhanced UARTs

KEY BENEFITS

• Increases program/data address range to 8 MB each

• Enhances performance and efficiency for C programs

• Fully 80C 51-compatible microcontroller

• Provides seamless and compelling upgrade path from classic 80C51

• Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs

• Supported by 80C51 development and programming tools

• The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market

COMPLETE FEATURES

•Fully static

• Up to 24 MHz CPU clock with 6 cloc k cycles per machine cycle

• 96 KB or 64 KB of on-chip OTP

• 3 KB or 2 KB of on-chip RAM

• 23-bit program memory space and 23-bit data memory space

• Four interrupt priority levels

• 32 I/O lines (4 ports)

• Three Timers: Timer0, Timer1 and Timer2

• Two full-duplex enhanced UARTs with baud rate generator

• Framing error detection

• Automatic address recognition

• Power control modes

• Clock can be stopped and resumed

• Idle mode

• Power down mode

• Second D PTR registe r

• Asynchronous port reset

• Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules

• Low EMI (inhibit ALE)

• Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)

80C51 COMPATIBILITY FEATURES OF THE 51MX CORE

• 100% binary compatibility with the classic 80C51 so that existing code is completely reusable

• Linear program and data address range expanded to support up to 8 MB each

• Program counter and data pointers expanded to 23 bits

• Stack pointer extended to 16 bits

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1.3 P87C51MX2 LOGIC SYMBOL

Data Bus

PORT0

Address Bus 0-7

RXD0 TXD0

INT0 INT1

T0 T1

PORT3

RXD1 TXD1

RST

/Vpp

PSEN ALE/PROG

P87C51Mx2

T2 T2EX ECI CEX0

PORT1

CEX1 CEX2 CEX3 CEX4

PORT2

Address Bus 8-15

XTAL2

XTAL1

Address Bus 16-22

Figure 1: P87C51Mx2 Logic Symbol

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1.4 P87C51MX2 BLOCK DIAGRAM

High Performance

80C51 CPU

(51MX Core)

96KB / 64KB

Code OTP

3KB / 2KB Data RAM

Port 3

Port 2

Port 1

UART 0

Internal Bus

Baud Rate

Generator

UART 1

Timer0 Timer1

Watchdog Timer

Crystal or

Resonator

Port 0

Oscillator

Figure 2: P87C51Mx2 Block Diagram

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PCA

(Programmable

Counter Array)

Timer2

Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

2 MEMORY ORGANIZATION

2.1 PROGRAMMER’S MODELS AND MEMORY MAPS

The P87C51Mx2 retain s all of the 80C 51 memory s paces. Additiona l memory sp ace has been a dded transpare ntly as part of the means for allowing extended addressing. The basic memory spaces include code memory (which may be on-chip, off-chip, or both); external data memory ; Special Function Reg isters; and inter nal data memory, whic h includes on-chip RAM, registers, and stack. Provision is made for internal data memory to be extended, allowing a larger processor stack.

The P87C51Mx2 programmer’s model and memory map is shown in Figure 3.

CODE

On-Chip and/or

Off-Chip

Code Memory

8 MB Code

Memory Space

7F:FFFFh

00:0000h

Two 24-bit Universal Pointers

23-bit Extended Data Pointer

Extended SFRs

Special Function

Registers

(directly addressable)

R5R6R7 R1R2R3

23-bit Program Counter

Two 16-bit DPTRs

16-bit Stack Pointer

EDATA

(includes DATA & IDATA)

Extended Data

Memory

(stack and indirect

addressing)

IDATA

(includes DATA)

256 Byte On-Chip

Data Memory

(stack and indirect

addressing)

DATA

128 Byte On-Chip

Data Memory

(stack, direct and indirect

addressing)

Four Register Banks

R0 - R7

Data Memory Space

(DATA, IDATA, EDATA)

HDATA

(includes XDATA)

7E:FFFFh

ABPSW

4FFh

Off-Chip

Data Memory

100h FFh

00:07FFh

80h 7Fh

XDATA

1792 Bytes On-Chip

Data Memory

(P87C51MC2)

XDATA

00:06FFh

00:0300h 00:02FFh

768 Bytes On-Chip

Data Memory

00h

(P87C51MB2)

00:0000h

8 MB - 64 KB External

Data Memory Space

(XDATA, HDATA)

Figure 3: P87C51MB2/C2 Programmer’s Model and Memory Map

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Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary. DATA 128 bytes of internal data memory space (00h...7Fh) accessed via direct or indirect addressing, using instructions

other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA Indirect Data. 256 bytes of internal data memory space (00h...FFh) accessed via indirect addressing using

instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

EDATA Extended Data. This is a superset of DATA and IDATA areas. Both P87C51MB2 and P87C51MC2 have 1280 bytes

of SRAM in EDATA memory. The added area may be accessed only as Stack and via indirect addressing using Universal Pointers. The Stack may reside in the extended area if enabled to do so.

SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via

direct addressing (addresses in range 80h...FFh). This includes the new 51MX extended SFRs.

XDATA "External" Data. Duplicates the classic 80C51 64 KB memory space addressed via the MOVX instruction using the

DPTR, R0, or R1. On-chip XDATA can be disabled under program control. Also, XDATA may be placed in external devices. P87C51MB2 has 768 bytes of on-chip XDATA memory space and P87C51MC2 has 1792 bytes of on-chip XDATA memory space.

HDATA "High" Data. This is a superset of XDATA and may include up to 8,323,072 bytes (8 MB - 64 KB) of memory space

addressed via the MOVX instruction u s ing the EPTR, DPTR, R0, or R1. Non XDATA portion of HDATA is placed in external devices.

CODE Up to 8 MB of Code memory, accessed as part of program execution and via the MOVC instruction. All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV

instruction. This feature is detailed in a subsequent section.

2.2 DATA MEMORY (DATA, IDATA, AND EDATA)

The standard 80C51 internal data memory consists of 256 bytes of DATA/IDATA RAM, and is always entirely on-chip. In this space are the data reg isters R 0 through R7, the de fault s tack, a bit address able RA M area, an d genera l purpos e data RAM. On the top of the DATA/IDATA memory space is a 1 KB block of RAM that can be accessed as stack or via indirect addressing. Alltogether this forms E DAT A RA M o f 12 80 b yte s. The different portions of the data m em ory are ac ces sed i n di fferent manners as described in the following sections.

2.2.1 REGISTERS R0 - R7

General purpose registers R0 thro ug h R7 a ll ow q ui ck , e ffi cie nt ac ce ss to a small number of internal data m emory loc ati ons . For example, the instruction:

MOV A,R0

uses one byte of code and executes in one machine cycle. Using direct addressing to accomplish the same result as in:

MOV A,10h

requires two bytes of code me mory and execut es in two machine cyc les. Indirect addres sing further require s setup of the pointer register, etc.

These registers are “bank ed”. The re are fou r grou ps of reg isters, an y one of whic h may b e sele cted to re presen t R0 throug h R7 at any particular time. Th is feature m ay be used to mi nimize th e time required fo r context s witching du ring an interru pt service or a subroutine, or to provide more register space for complicated algorithms.

The registers are no different from other internal data memory locations except that they can be addressed in "shorthand" notation as "R0", "R1", etc. Instructions addressing the internal data memory by other means, such as direct or indirect addressing, are quite capable of accessing the same physical locations as the registers in any of the four banks.

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2.2.2 BIT ADDRESSABLE RAM

Internal data memory locations 20 hex through 2F hex may be accessed as both bytes and bits. This allows a convenient and efficient way to manipulate individual flag bits without using much memory space. The bottom bit of the byte at address 20h is bit number 00h, the next bit in the same byt e is bi t num ber 01 h, etc . The fin al bi t, bit 7 of the byte at addre ss 2Fh, is bit number 7Fh (127 decimal). Bit numbers above this refer to bits in Special Function Registers.

This code:

SETB 20h.1 CPL 20h.2 JNB 20h.2, LABEL1

sets bit 1 at address 20 hex, complements bit 2 in the same byte, then branches if the second bit is not equal to 1. In an actual program, these bits would normally be given names and referred to by those names in the bit manipulation instructions.

2.2.3 EXTENDED DATA ME MORY (EDATA)

The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic 80C51s. This space can be used as an extended or alternative processor stack space, or can be used as general purpose storage under program control. Other than Stack Pointer based access to this space, which is automatic if Extended Stack Memory Mode is enabled (see the following Stack section), this memory is addressed only using the new Universal Pointer feature. Universal Pointers are described in a later section.

Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory.

2.2.4 STACK

The processor stack pr ovide s a mean s to sto re interru pt and s ubrouti ne return a ddress es, as well as te mporar y data. Th e stac k grows upwards, fro m lower addresse s towards higher addresses. The current Stack Poin ter always points to the last ite m pushed on the stack, unless the stack is empty. Prior to a push operation, the Stack Pointer is incremented, then data is written to memory. When the stack is popped, the reverse procedure is used. First, data is read from memory, then the Stack Pointer is decremented.

The default configurat ion of the 51 MX stack is iden tical to the cl assic 80C5 1 stack imp lementati on. When inte rrupt or subrouti ne addresses are pushed onto the stack, onl y the lower 16 bi ts of the Progra m Coun ter are stored. Thi s defaul t 80C51 mode stack operation is shown in Figure 4.

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0083h 0082h

Final SP Value (afte r ACALL, LCALL or Interrupt)

Initial SP Value (before ACALL, LCALL, or interrupt)

This figure applies to th e ACALL and LCALL instructions in all modes. In 80C51 stack mo d e, i t al so applies to interrupt processing.

Figure 4: Return Address Storage on the Stack (80C51 Mode)

PCH (PC.15-8)

PCL (PC.7-0)

0081h 0080h 007Fh

There are two configuratio n op tions fo r the stac k. For purp oses of backwa rd comp atibil ity with the class ic 80C5 1, both al ternate modes are disabled by a c hip re set. Th e first option , Exten ded Int errupt Fra me Mo de, ca uses interru pts to p ush the e ntire 2 3-bi t Program Counter onto the stack (as three bytes), and the RETI instruction to pop all 23-bits as a return address, as shown in Figure 5. The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a "1" to be consistent with Universal Pointer addressing.

Storing the full 23-bit Program Counter value is a requirement for systems that include more than 64 KB of program, since an interrupt could occur at any point in the program. The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruct ion on ly, whi le oth er cal ls and returns are n ot affe cted. Sp ecial exte nded c all a nd retur n inst ruction s all ow large programs to trave rse the entire code sp ac e w i th ful l 2 3-bi t return addresses. T he Ext end ed Interrupt Frame Mod e i s ena bl ed by setting the EIFM bit in the MXCON register.

This figure applies to interrupt services in Extended Interrupt Frame Mode, as well as the ECALL instruction in all modes.

The upper bit of the byte containing PCE is forced to a "1" in order to be consistent with Universal Pointers.

PCE (PC.22-16)

PCH (PC.15-8)

PCL (PC.7-0)

0083h 0082h 0081h 0080h 007Fh

Final SP Value (after ECALL or interrupt)

Initial SP Value (before ECALL or interrupt)

Figure 5: Extended Return Address Storage on the Stack

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The second stack option, Extended Stack Memory Mode, allows for stack extension beyond the 256 byte limit of the classic 80C51 family. Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory. Stack extension has no effect on the data that is stored on the stack, it will continue to be stored as shown on in figures 4 and 5. The Extended Stack Memory Mode is enabled by setting the ESMM bit in the MXCON register.

If the Stack Point er i s not in itia li zed b y s of tw are, the s tac k w ill be gi n a t on-chip RAM address 8, just as for the 80 C51. Als o note that in Extended Stack Memory Mode, both MB2 and MC2 parts have 1KB of RAM on the top of DATA/IDATA space available for the stack.

The stack mode bits ESMM and EIFM are shown in Figure 6. Note that the stack mode bits are intended to be set once during program initialization and not altered after that point. Changing stack modes dynamically may cause stack synchronization problems.

MXCON

Not bit addressable Reset Value: 00h

BIT SYMBOL FUNCTION

MXCON.7 - 3 - Reserved. Programs should not write a 1 to these bits. MXCON.2 EAM Enabl es Extended Add ressing Mod e, in connecti on with a non-volat ile user config uration

MXCON.1 ESMM Enables the Extende d Stack Me mory M ode. W hen ESMM = 0, the Stack Pointer i s 8 bit s

MXCON.0 EIFM Enables the Extended Interrupt Frame Mode. When EIFM = 0, an interrupt service will

Address: FFh (51MX Extended SFR Space)

76543210

- - - - - EAM ESMM EIFM

bit. The logical OR of the SFR bit and the non-volatile conf iguration bit deter mines whether code and data addressing beyond 64 KB is allowed. The same logical OR value will be read from this bit by software. When 0, all addressing (on-chip and off-chip) is limited to 64 KB each of code and data. When 1, 51MX addressing capabilities are extended beyond boundary of 64 KB to 8 MB each of code and data, and upper address bits are multiplexed on Port 2 for external code and/or data accesses. Refer to the External Bus section for additional details.

EAM must be set to EAM=1 if at least one of the next two statements is true:

- there is executable code or constants in CODE space are above 64 KB

- address of data byte that has to be accessed in HDA TA is above 64 KB

in width and the sta ck is located in the IDATA m emory space. W hen ESMM = 1, th e Stack Pointer is increased to 16-bits in width and the stack may be located anywhere in the EDATA space. ESMM is independent of EAM and EIFM bits.

cause only the lower 16 bits of the PC to be pushed onto the stack, and an RETI instruction will restore only the lower 16 bits of the PC. When EIFM = 1, an interrupt service will cause all 23 bits of the PC to be pushed onto the stack, while an RETI instruction will restore all 23 bits of the PC. EIFM must allows execution beyond the first 64 KB of code memory.

be set to one if the application

Figure 6: MX Configuration Register (MXCON)

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2.2.5 GENERAL P URPOSE RAM

Portions of the intern al data mem ory tha t are not used i n a parti cular a pplic ation a s registers , stac k, or bit addr essable locations may be considered general purpose RAM and used in any desired manner.

The lower 128 bytes of the internal data memory (DATA) may be accessed using either direct or indirect addressing. Direct addressing incorporates the entire address within the instruction. For example, the instruction:

MOV 31h,#10

will store the value 10 (decimal) in location 31 hex. Direct addresses above 128 will access the Special Function Registers rather than the internal data memory.

Indirect addressing takes an address from either R0 or R1 of the current register bank and uses it to identify a location in the internal data memory. The ent ire 256 byt e internal d ata memo ry space (I DATA) may be a ccessed us ing indire ct addres sing. For example, the instruction seq uen ce :

MOV R0,#90h MOV A,@R0

will cause the conte nts of locatio n 90 hex to be loa ded into the accum ulator. It is typ ical with the classic 80C51 to c ause the stack to be located in the upper area, leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect add ressing. With t he 51MX, the stack may b e extended a nd moved c ompletely ou t of the low er 256 byte s of memory.

8 Bytes

7F 77 6F 67 5F 57 4F 47 3F 37

bit 7F …

2F 27 1F 17 0F 07

Figure 7: Internal Data Memory, Lower 128 Bytes

bank 3 bank 2 bank 1 bank 0

… bit 0

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00

Undedicated

Area

Bit Addressable

Segment

Banks

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2.3 SPECIAL FUNCTION REGISTERS (SFRS)

Special Function Registers (SFRs) provide a means for the processor to access internal control registers, peripheral devices, and I/O ports. An SFR address is always contained entirely within an instruction.

The standard SFR sp ace is 1 28 bytes in size . SFRs are i mplemen ted in each 51MX dev ice as n eeded in order to pro vide con trol for peripherals or access to CPU features and func tions. Undefined SFR s are considered "res erved" and should not b e accessed by user prog rams.

Sixteen addresses in the SFR space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0h or 8h (i.e. 80h, 88h, ..., F8h). Bit addressing allows direct control and testing of bits in those SFRs.

All 51MX devices also have ad ditional 128 by tes of extended SFRs as discussed in the "51MX Architectu re Reference". Figure s 8 and 9 show the SFR and the Extended SFR maps for P87C51MB2/C2 parts.

0 / 8 1 / 9 2 / A 3 / B 4 / C 5 / D 6 / E 7 / F F8 F0 E8 E0 D8 D0 C8 C0 C7 B8 B0 A8 A0 98 90 88 80

Bit Addressable SFRs

IP1 CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H FF

B IP1H F7 IEN1 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L EF ACC E7

CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF

PSW D7

T2CON T2MOD R2CAPL R2CAPH TL2 TH2 CF

IP0 S0ADEN BF

P3 IP0H B7

IEN0 S0A DDR AF

P2 AUXR1 WDRST A7

S0CON S0BUF 9F

P1 97

TCON TMOD TL0 TL1 TH0 TH1 AUXR 8F

P0 SP DPL DPH PCON 87

↑

Figure 8: Standard SFR Map for the P87C51Mx2

Figure 9 shows the extended SFR map for the P87C51Mx2.

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Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

0 / 8 1 / 9 2 / A 3 / B 4 / C 5 / D 6 / E 7 / F F8 F0 F7 E8 EF E0 E7 D8 DF D0 D7 C8 CF C0 C7 B8 BF B0 B7 A8 AF A0 A7 98 9F 90 97 88 80

S1CON S1BUF S1ADDR S1ADEN S1STAT BRGCON BRGR0 BRGR1 87

Bit Addressable SFRs

↑

SPE EPL EPM EPH MXCON FF

S0STAT WDCON 8F

Figure 9: Extended SFRs Map for the P87C51Mx2

2.4 EXTERNAL DATA MEMORY (XDATA)

The XDATA space on the 51MX is the same as the 64 KB external data memory space on the classic 80C51. On-chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register. Accesses above

implemented on-chip XDATA w i ll b e rou ted to th e ex ter nal bus . If o n-c hip XDATA m em ory is dis ab led , al l XDATA a cc es ses wil l be routed to the external bus. P87C51MB2 has 768 bytes of on-chip XDATA, while P87C51MC2 has 1792 bytes of on-chip XDATA memory.

2.5 HIGH DATA MEMORY (HDATA)

The 51MX architecture supports up to an 8 MB data memory space, using 23-bit addressing. The entire 8 megabyte space except for the 64 KB EDATA space is called HDATA. The XDATA space comprises the lower 64 KB of HDATA.

Data Pointers

The 51MX adds an addition al 23-bit Extended Data Pointer (EPTR) in order to allow a simple metho d of extending existing 80C51 programs to use mo re than 64 KB of data mem ory. If we wa nt to access a sin gle d ata by te from HDATA RAM locate d abo ve the first 64 KB, EAM bit in MXCON sfr must be set to EAM=1.

All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR. The 23-bit EPTR is comprised of (in order) EPH, EPM, and EPL. Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR respectively. Since th e EPTR i s a 23 -bit va lue , th e 8 th b it o f EPH is not used. If read, it will ret urn a 1, like other unimplemented bits in SFRs. Use of the EPTR allows access to the entire HDATA space, including XDATA.

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P87C51Mx2Extended Address Range Micr ocontroller

At any point in time, one specific Data Pointer is active and is used by instructions that reference the DPTR. The active DPTR may be changed by altering th e Data Pointer Select (DPS) bit. The DPS bit occupies the bo ttom bit of the AUXR 1 re gis ter. The DPS bit applies only to the two DPTRs, not to the EPTR.

In the indirect addressing mode, the currently active DPTR or the EPTR provides a data memory address for accessing the XDATA and HDATA space res pe ctive ly . Whe n th e D PTR i s used for a ddre ss in g, o nly the XDATA s pac e i s a vaila ble . Whe n th e EPTR is used for addressing , the entire HD ATA spac e (which inc ludes the XDATA sp ace) may be ac cess ed. If the EPTR value exceeds 7E:FFFF (the limit of HDATA), data accesses using EPTR will yield undefined results. The reason for limiting HDATA addresses is to keep the add ressing uniform for EPTR addressing and Un iversal Pointer addres sing (which is expl ained in a later section of this document).

Example Instruction:

MOVX @DPTR,A

Figure 10: External Data Memory Access using Indirect Addressing with DPTR

Example Instruction:

MOVX A,@EPTR

DPS

Data Pointers 0 = A17Ch 1 = 2962h

(00:A17Ch)

External Data

Memory

Location

00:A17Ch:

33h

External Data

Memory

Accumulator

33h

EPTR

0 = 01:1034h

Figure 11: External Data Memory Access using Indirect Addressing with EPTR

Location

01:1034h:

3Bh

Accumulator

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3Bh

Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

2.6 PROGRAM MEMORY (CODE)

The 80C51, and th us the 51M X, ar e "Harv ard" a rchite ctures , mea ning t hat the cod e and data space s are separ ated. I f th ere is a single byte of executable code above 64 KB, EAM bit in MXCON sfr must be set to EAM=1. Also, if there is constant in CODE space above 64 KB boundary that is read by the application, EAM must be set to EAM=1, too.

The 51MX expands t he 80C5 1 Program C ounter t o 23 bits , providi ng a con tiguous, unsegme nted line ar code spa ce that m ay be as large as 8 MB. On-chip space begi ns at cod e address 0 and exten ds to the limit of the on-chip code me mory. Above th at, code will be fetched from off-chip. The 51MX architecture allows for an external bus which supports:

• Mixed mode (some code and/or data memory off-chip).

• Single-chip operation (no external bus connection).

• ROMless operation (no use of on-chip code memory). In some cases, c ode memory m ay be address ed as data. Exte nded instruct ion address m odes provide access to th e entire code

space of 8 MB thro ugh th e use o f inde xed i ndirect add ressing. The c urrentl y act ive DP TR, th e EP TR, a U niversa l P ointer, or the Program Counter may be used as the base address. Examples of the various code memory addressing modes are shown in figures 12 through 14.

Following a reset, t he 51MX begin s code execut ion like a c lassic 80C51 , at address 00:0000h. Similarly, the in terrupt vectors are placed just above the res et addre ss, start ing at add ress 00:0 003h. I t is im portan t to not e that f irst in struct ion (located at a ddress

0) should not be an EJMP instruction. EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt 0 vector address.

Example Instruction:

MOVC A,@A+PC

Figure 12: Code Memory Access using Indexed Indirect Addressing with the Program Counter

3E:97FFh

Accumulator

D3h

(3E:98D2h)

Code

Memory

Location

3E:98D2h:

70h

Accumulator

70h

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P87C51Mx2Extended Address Range Micr ocontroller

Example Instruction:

MOVC A,@A+DPTR

executed at address 01:59B3

DPS

Example Instruction:

MOVC A,@A+EPTR

Data Pointers 0 = C340h 1 = FF0Ch

Figure 13: Code Memory Access using Indexe d Indir ect Addr es sing with DPTR

Accumulator

A2h

(FFAEh)

Upper 7 bits of

Program Counter

(01h)

01:FFAEh

01:FFAEh:

Code

Memory

Code

Memory

Location

C1h

Accumulator

C1h

Accumulator

CDh

EPTR

12:B109h

(12:B1D6h)

Figure 14: Code Memory Access using Indexed Indirect Addressing with EPTR

Location

12:B1D6h:

55h

Accumulator

55h

2.7 UNIVERSAL POINTERS

A new addressing mode called Universal Pointer mode has been added to the 51MX, specifically for the purpose of greatly enhancing C langua ge code density and performance. This addressing mo de allows access to any of the on-chip or off-chip code and data spaces usi ng one i nstruc tion, w ithou t the ne ed to kn ow in advan ce whic h of the differe nt spac es the data w ill re side in. This includes the DATA, IDATA, EDATA, XDATA, HDATA, and CODE spaces. The SFR space is the only space that may not be accessed using the Universal Pointer mode.

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P87C51Mx2Extended Address Range Micr ocontroller

The Universal Pointer addressing mode uses a new set of pointer registers for two reasons. The first is that 24-bit pointers are needed in order to allow address ing both the 8 MB code space and the 8 MB data spac e. The other reason is that it is much more efficient to manipulate multi-byte pointer values in registers than it is in SFRs. C compilers typically already perform pointer manipulation in registers, then move the result to a Data Pointer for use.

Two Universal Pointers are supported: PR0 and PR1. The pointer PR0 is composed of registers R1, R2, and R3 of the current register bank, while PR1 is composed of registers R5, R6, and R7 of the current register bank, as shown in Figure 15.

PR0

MSB LSB

R3 R2 R1

Figure 15: Universal Pointer Registers

In order to access all of the various memory spaces in a single unified manner, they must all be mapped into a new "view" that allows 16 MB of total memory space. This new view is called the Universal Memory Map.

The XDATA space is placed at th e bottom of this ne w addres s map. Th e HDATA sp ace co ntinue s abov e XDATA. The sta ndard internal data memory space s (DATA and IDATA) are above HD ATA, followed by the remainder of the EDATA sp ace. Finally, the code memory occupies the top of the map.

Thus, the most significant bit of the Universal Pointer determines whether code or data memory is accessed. By placing the XDATA space at the bottom of the Universal Memory Map, Universal Pointer addresses 00:0000 through 00:FFFF can correspond to the classic 80C5 1 ex tern al da ta m em ory spa ce . Thi s al lows for full backward compatibili ty fo r co de th at do es not need more than 64 KB o f exte rnal da ta spac e. The Univers al Me mory M ap is shown i n Figu re 16, w hile the sta ndard v iew of th e memory spaces and how they relate to Universal Pointer values are shown in Figure 17.

The Universal Pointers are used only by a new 51MX instruction called EMOV. The EMOV instruction allows moving data via one of the Univers al Poin ters i nto or out of t he ac cumul ator. In eithe r case , a di splac ement of 0, 1, 2, o r 3 may als o be spec ified, which is added to th e pointer pr ior to its use. T he displace ment allows C c ompiler acc ess of variables of up to 4 b ytes in size (e. g. Long Integers) without the need to alter the pointer value. An example of Universal Pointer usage is shown in Figure 18. Note that it is not possible to store a value to the CODE area of the Universal Memory Map.

MSB LSB

R7 R6 R5

PR1

Another new instruction is added to allow incrementing one of the Universal Pointers by a value from 1 to 4. This allows the pointer to be advanced past the last data element accessed, to the next data element.

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Memory Space Addressing Modes

FF:FFFFh

CODE

EDATA

IDATA

DATA

Up to 8 MB

on-Chip and/or off-Chip

program memory

Up to 64 KB - 256 bytes

on-chip and/or off-chip da ta

accessed as Stack and via

Universal Pointer only

Upper 128 bytes

on-chip indirectly address ed

RAM

Lower 128 bytes

on-chip directly & indirectly

addressed RAM

80:0000h 7F:FFFFh

7F:0100h 7F:00FFh

7F:0080h 7F:007Fh

7F:0000h 7E:FFFFh

PC, PC relative addressing DPTR (lower 64 KB of Code ) EPTR Universal Pointers: PR0, PR1

Stack (SPE / SP) Universal Pointers: PR0, PR1

R0, R1 Stack (SPE / SP) Universal Pointers: PR0, PR1

Direct add ressing R0, R1 indirect Stack (SPE / SP) Universal Pointers: PR0, PR1

HDATA

XDATA

Up to 8 MB - 128 KB

data accessed via MOVX

(generally off-chip data)

01:0000h 00:FFFFh

Up to 64 KB

on-chip and/or off-chip

data accessed via MOVX

00:0000h

Figure 16: Universal Memory Map

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R0, R1 (lower 256 bytes

on-chip, lower 64 KB off-chip via use of P2) DPTR (XDATA access only) EPTR (HDATA access) Universal Pointers: PR0, PR1

Philips Semiconductors P87C51Mx2 User Manual

P87C51Mx2Extended Address Range Micr ocontroller

16MB

CODE

EDATA

IDATA

DATA

8MB

DATA,

IDATA,

EDATA

HDATA

HDATA,

XDATA

24-bit Addressing using PR1 and PR2Standard Memory Map

Figure 17: Mapping of other Addressing Modes to Universal Pointer Addressing

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Example Instruction:

EMOV @PR0+1,A

PR0

12:C340h

(12:C341h)

Figure 18: Memory Access using Universal Pointer Addressing

Universal Pointers a re desi gned prim arily to fa cilitate a ddressing in Extend ed Addressing Mode, wi th the EAM bi t in MXCON s et to one. However, Universal Pointers may still be used when EAM = 0. In this case, Universal Pointer addressi ng can access only the bottom 64 KB of the Code sp ace, th e 64 KB XD ATA space, a nd the 64 KB EDATA sp ace. The U niver sal Poi nter value s that point to these areas do not change. When EAM = 0, Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex.

Universal

Memory Map

Location

12:C341h:

39h

Accumulator

39h

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3 51MX INSTRUCTIONS

The 51MX instruction set is a a true binary-level superset of the classic 80C51, designed to be fully compatible with previously written 80C51 code. The changes to the instruction set are all related to the expanded address space. Some details of existing instructions have been altered , and some instru ction s have had an extended mode added. In the la tter case, the alternate mo de of the instruction is activated by preceding the instruction with a special one-byte prefix code, A5h.

An important goal i n t he i mp lem en tat ion of the 51MX was to ke ep the same timing relation sh ip o f ex is ti ng 8 0C 51 in structions to existing devices. Any 80C51 instruction executed on the 51MX will take the same number of machine cycles to execute.

80C51 Instruction Effect of Extended Addressing

All relative branches

Includes SJMP and all cond itional branches . These instruct ions may cross a 64 KB bound ary if they are located within branch range of the boundary.

ACALL addr11

AJMP addr11

JMP @A+DPTR

MOVC A,@A+DPTR

MOVC A,@A+PC

MOVX @DPTR,A The active DPTR points to an address in the 64 KB XDATA memory. MOVX A,@DPTR The active DPTR points to an address in the 64 KB XDATA memory.

RET

RETI

LCALL addr16

This instruction wil l cross a 64 KB bo undary if it is loc ated such tha t the next inst ruction in seq uence is across the boundary.

The lower 16-bits of the Program Counter are replaced with the value formed by the sum of the Accumulator and the active DPTR. This instruction will cro ss a 64 KB b oundary if it is loc ate d suc h that the next instruction in sequence is across the boundary.

The address formed by replacing the lower 16-bits of the Program Counter with the value formed by the sum of the Ac cumulato r and the active D PTR is us ed to ac cess c ode memo ry. The PC v alue used is that of the instruction following MOVC.

The sum of the Accumula tor and the 23 -bit Progr am Counter fo rms the 23-b it address us ed to read the code memory. The PC value used is that of the instruction following MOVC.

Replaces the lower 16 bits of the Program Counter with a 16-bit address from the Stack. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

When the extended interrupt frame mode is not ena ble d, th is ins tru cti on r eplaces the lower 16 bits of the Program Counter with a 16-bit address from the Stack. This will cause a 64 KB boundary to be crossed if the instruction is located such that the next instruction in sequence is across the boundary. If the extended interrupt frame mode is enabled, a 23-bit address is loaded into the PC from the stack.

Replaces the lower 16 bi ts of the Program Counter with th e 16-bit address. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

LJMP addr16

Table 1: Instructions Affected by Extended Address Space

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P87C51Mx2Extended Address Range Micr ocontroller

80C51 Instruction

LCALL addr16

LJMP addr16

JMP @A+DPTR

MOVC A,@A+DPTR

MOVX @DPTR,A

MOVX A,@DPTR

INC DPTR

MOV DPTR,#data16

RET

ORL A,Rn

ANL A,Rn

XRL A,Rn

51MX Effect

Without Prefix

Load a 16-bit address into the Program Counter.

The lower 16-bits of the Program Counter are replac ed with the sum of the Accumulator and the active DPTR.

Code memory is accessed using the address form ed by replacing the lower 16-bits of the Program Counter with the sum of the Accumulator and the active DPTR.

The active DPTR points to an address in the 64 KB XDATA memory.

Increment the active Data Pointer.

Load a 16-bit value into the active Data Pointer.

Load a 16-bit address into the Program Counter from the Stack.

Logically OR Register n to the Accumulator.

Logically AND Regis ter n to the Accumulator.

Exclusive OR Reg ister n to the Accumulator.

51MX Enhancement

(these instructions use

the prefix byte)

ECALL addr23

EJMP addr23

JMP @A+EPTR

MOVC A,@A+EPTR

MOVX @EPTR,A

MOVX A,@EPTR

INC EPTR Increment the 23 bit EPTR.

MOV EPTR,#data23 Load a 23-bit value into the EPTR.

ERET

EMOV A,@PRi+disp

EMOV @PRi+disp,A

ADD PRi,#data2

Load a 23-bit address into the Program Counter.

The Program Counter is loaded with the value formed by th e sum of the Accumu lator and the EPTR.

Code memory is accessed using the address formed by the sum of the Accumulator and the EPTR.

The EPTR points to an addre ss anywhere in HDATA memory (not DATA, IDATA, or EDATA).

Load a 23-bit address into the Program Counter from the Stack.

Load the Accumulator with the value from the Universal Memory Map at the address formed by PR0 or PR1plus the displacement (a value fr om 0 to 3).

Load the Universal Memory Map address formed by PR0 or PR1 plus the displacement (a value from 0 to 3) with the contents of the Accumulator.

Add an immediate data va lue fr om 1 to 4 to the specified Univers al Pointer. This is a 24bit addition.

51MX Effect with Prefix

Table 2: Enhancements to the 80C51 Instruction Set Enabled by the Prefix Byte

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