Philips P87C748EBPN, P87C748EBDDB, P87C748EBAA, P83C748EBPN, P83C748EBDDB Datasheet

INTEGRATED CIRCUITS

83C748/87C748

80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

Preliminary specification Supersedes data of 1998 Apr 23 IC20 Data Handbook

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1999 Apr 15

Philips Semiconductors Preliminary specification

80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

DESCRIPTION

The Philips 83C748/87C748 offers the advantages of the 80C51 architecture in a small package and at low cost.

The 8XC748 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity.

The 8XC748 contains a 2k × 8 ROM (83C748) EPROM (87C748), a 64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a four-source, fixed-priority level interrupt structure, and an on-chip oscillator.

FEA TURES

•80C51 based architecture

•Small package sizes

– 24-pin DIP (300 mil “skinny DIP”) – 24-pin Shrink Small Outline Package (SSOP) – 28-pin PLCC

•87C748 available in erasable quartz lid or one-time programmable

plastic packages

•Wide oscillator frequency range: –3.5 to 16MHz

•Low power consumption:

– Normal operation: less than 11mA @ 5V, 12MHz – Idle mode – Power-down mode

•2k × 8 ROM (83C748)

2k × 8 EPROM (87C748)

•64 × 8 RAM

•16-bit auto reloadable counter/timer

•10-bit fixed-rate timer

•Boolean processor

•CMOS and TTL compatible

•Well suited for logic replacement, consumer and industrial

applications

•LED drive outputs

PIN CONFIGURATIONS

P3.4/A4

P3.3/A3

RST

X2 X1

4 5

6 7 8

9 10 11 12

4126

12 18

P3.2/A2/A10

P3.1/A1/A9 P3.0/A0/A8

P0.2/V

P0.1/OE–PGM

P0.0/ASEL

Pin Function

1 P3.4/A4 2 P3.3/A3 3 P3.2/A2/A10 4 P3.1/A1/A9 5 NC* 6 P3.0/A0/A8 7 P0.2/V 8 P0.1/OE-PGM 9 P0.0/ASEL

10 NC*

11 RST 12 X2 13 X1

* NO INTERNAL CONNECTION

14 V

83C748/87C748

P3.5/A5

23 22

P3.6/A6

PLASTIC

DUAL

IN-LINE

AND

SHRINK

SMALL

OUTLINE

PACKAGE

PLASTIC LEADED

CHIP

CARRIER

P3.7/A7

P1.7/T0/D7 P1.6/INT1/D6

19 18

P1.5/INT0

P1.4/D4

P1.3/D3

P1.2/D2

P1.1/D1

P1.0/D0

Pin Function

15 P1.0/D0 16 P1.1/D1 17 P1.2/D2 18 P1.3/D3 19 P1.4/D4 20 P1.5/INT0 21 NC* 22 NC* 23 P1.6/INT1/D6 24 P1.7/T0/D7 25 P3.7/A7 26 P3.6/A6 27 P3.5/A5 28 V

/D5

SU00295A

ORDERING INFORMATION

ROM EPROM

TEMPERATURE RANGE °C

AND PACKAGE

P83C748EBP N P87C748EBP N OTP 0 to +70, Plastic Dual In-line Package 3.5 to 16 SOT222-1 P83C748EBA A P87C748EBA A OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16 SOT261-3

P83C748EBD DB P87C748EBD DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16 SOT340-1

NOTE:

1. OTP = One Time Programmable EPROM.

1999 Apr 15

FREQUENCY

MHz

DRAWING

NUMBER

Philips Semiconductors Preliminary specification

80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count

BLOCK DIAGRAM

RAM ADDR

RAM

ACC

TMP2

PSW

ALU

P0.0–P0.2

PORT 0

DRIVERS

PORT 0

LATCH

TMP1

PCON TCON

TH0 TL0 RTH RTL

INTERRUPT AND

TIMER BLOCKS

STACK

POINTER

ROM/

EPROM

83C748/87C748

PROGRAM

ADDRESS

BUFFER

INCRE-

MENTER

RST

TIMING

AND

CONTROL

OSCILLATOR

INSTRUCTION

PORT 1

LATCH

PORT 1

DRIVERS

P1.0–P1.7

PORT 3

LATCH

PORT 3

DRIVERS

P3.0–P3.7

PROGRAM COUNTER

DPTR

SU00296

1999 Apr 15

Philips Semiconductors Preliminary specification

80C51 8-bit microcontroller family

83C748/87C748

2K/64 OTP/ROM, low pin count

PIN DESCRIPTIONS

PIN NO.

MNEMONIC

P0.0–P0.2 8–6 9–7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,

P1.0–P1.7 13–20 15–20,

P3.0–P3.7 5–1,

RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to V (e.g. 2k).

ABSOLUTE MAXIMUM RATINGS

Storage temperature range –65 to +150 °C Voltage from V Voltage from any pin to V Power dissipation 1.0 W Voltage on VPP pin to V Maximum IOL per I/O pin 10 mA

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

DIP/

SSOP

23–21

LCC TYPE NAME AND FUNCTION

12 14 I Circuit Ground Potential 24 28 I Supply voltage during normal, idle, and power-down operation.

and in that state can be used as high-impedance inputs. These pins are driven low if the port register bit is written with a 0. The state of the pin can always be read from the port register by the program.

P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0

also provides alternate functions for programming the EPROM memory as follows: 6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1). 7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.

8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.

23, 24

18 20 I INT0 (P1.5): External interrupt. 19 23 I INT1 (P1.6): External interrupt. 20 24 I T0 (P1.7): Timer 0 external input.

6, 4–1,

27–25

to V

(except VPP) –0.5 to VCC + 0.5 V

OE/PGM = 1 output enabled (verify mode).

OE/PGM = 0 program mode.

ASEL = 0 low address byte available on port 3.

ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins

that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical

Characteristics: I

accepts as inputs the value to program into the selected address during the program mode. Port 1

also serves the special function features of the 80C51 family as listed below:

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins

that are externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: I

programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.

An internal diffused resistor to V

. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places

the device in the programming state allowing programming address, data and V

programming or verification purposes. The RESET serial sequence must be synchronized with the

X1 input.

X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the

programming state.

1, 2

PARAMETER

). Port 1 serves to output the addressed EPROM contents in the verify mode and

). Port 3 also functions as the address input for the EPROM memory location to be

permits a power-on RESET using only an external capacitor to

to be applied for

via a small pull-up

RATING UNIT

–0.5 to +6.5 V

0 to +13.0 V

1999 Apr 15

Philips Semiconductors Preliminary specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

80C51 8-bit microcontroller family

83C748/87C748

2K/64 OTP/ROM, low pin count

DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, VCC = 5V ±10%, VSS = 0V

amb

IH1

IL1

IH2

OL1

OL2

C Capacitance 10 pF I

RST

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

2. Under steady state (non-transient) conditions, I

If I

test conditions.

3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

4. Power-down I

5. Active I RST = port 0 = V

6. Idle I port 0 = V

Input low voltage –0.5 0.2VDD–0.1 V Input high voltage, except X1, RST 0.2VCC+0.9 VCC+0.5 V Input high voltage, X1, RST 0.7V

P0.2 Input low voltage –0.5 0.3V Input high voltage 0.7V

Output low voltage, ports 1 and 3 IOL = 1.6mA Output low voltage, port 0.2 IOL = 3.2mA

Output high voltage, ports 1 and 3 IOH = –60µA 2.4 V

Port 0.0 and 0.1 – Drivers Output low voltage IOL = 3mA 0.4 V Driver, receiver combined: (over VCC range)

Logical 0 input current, ports 1 and 3 VIN = 0.45V –50 µA Logical 1 to 0 transition current, ports 1 and 3 Input leakage current, port 0 0.45 < VIN < V

Internal pull-down resistor 25 175 kΩ Pin capacitance Power-down current

VPP program voltage (for 87C748 only)

Program current (for 87C748 only) VPP = 13.0V 50 mA Supply current (see Figure 2)

Maximum I Maximum I Maximum total I

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

is measured with all output pins disconnected; X1 driven with t

; RST = VSS.

per port pin: 10mA

per 8-bit port: 26mA

for all outputs: 67mA

is approximately 2V .

is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.

. ICC will be slightly higher if a crystal oscillator is used.

VIN = 2V (0 to 70°C) –650 µA

Test freq = 1MHz,

VCC = 2 to VCC max 50 µA

amb

must be externally limited as follows:

CLCH

, t

CLCH

LIMITS

MIN MAX

VCC+0.5 V

0.45 V

±10 µA

10 pF

2 2

IOH = –25µA 0.75V IOH = –10µA 0.9V

= 25°C

amb

VSS = 0V

= 5V±10%

= 21°C to 27°C

, t

= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;

CHCL

= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;

CHCL

12.5 13.0 V

unless otherwise

V V

1999 Apr 15

Philips Semiconductors Preliminary specification

80C51 8-bit microcontroller family

83C748/87C748

2K/64 OTP/ROM, low pin count

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, VCC = 5V ±10%, VSS = 0V

amb

SYMBOL PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

Oscillator frequency: 3.5 12 MHz

External Clock (Figure 1)

CHCX

CLCX

CLCH

CHCL

High time 20 20 ns Low time 20 20 ns Rise time 20 20 ns Fall time 20 20 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

2. Load capacitance for ports = 80pF.

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: C – Clock D – Input data H – Logic level high

1, 2

16MHz CLOCK VARIABLE CLOCK

3.5 16 MHz

L – Logic level low Q – Output data T – Time V – Valid X – No longer a valid logic level Z – Float

unless otherwise

CHCL

CLCX

CLCL

CLCH

CHCX

SU00297

VCC –0.5

0.45V

0.2 V

+ 0.9

– 0.1

Figure 1. External Clock Drive

ROM CODE SUBMISSION

When submitting ROM code for the 83C748, the following must be specified:

1. 2k byte user ROM data

ADDRESS

0000H to 07FFH DATA 7:0 User ROM Data

CONTENT BIT(S) COMMENT

1999 Apr 15

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