Philips p80cl51 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
P80CL31; P80CL51
Low voltage 8-bit microcontrollers
with UART
Product specification
Supersedes data of January 1995
File under Integrated circuits, IC20
1997 Apr 15
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
2.1 Versions: P80CL31 and P80C51
3 APPLICATIONS
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 FUNCTIONAL DIAGRAM
7 PINNING INFORMATION
7.1 Pinning
7.2 Pin description
8 FUNCTIONAL DESCRIPTION OVERVIEW
8.1 General
8.2 CPU timing
9 MEMORY ORGANIZATION
9.1 Program Memory
9.2 Data Memory
9.3 Special Function Registers (SFRs)
9.4 Addressing
10 I/O FACILITIES
10.1 Ports
10.2 Port options
10.3 Port 0 options
10.4 SET/RESET options
11 TIMERS/EVENT COUNTERS
12 REDUCED POWER MODES
12.1 Idle mode
12.2 Power-down mode
12.3 Wake-up from Power-down mode
12.4 Power Control Register (PCON)
12.5 Status of external pins
13 STANDARD SERIAL INTERFACE SIO0:
UART
13.1 Multiprocessor communications
13.2 Serial Port Control and Status Register
(S0CON)
P80CL31; P80CL51
13.3 Baud rates
14 INTERRUPT SYSTEM
14.1 External interrupts INT2 to INT9
14.2 Interrupt priority
14.3 Interrupt registers
15 OSCILLATOR CIRCUITRY
16 RESET
16.1 External reset using the RST pin
16.2 Power-on-reset
17 MASK OPTIONS FOR P80CL31 AND P80C51
17.1 P80CL31: ROMless version
17.2 P80C51: 5V standard version
18 SPECIAL FUNCTION REGISTERS
OVERVIEW
19 INSTRUCTION SET
20 LIMITING VALUES
21 DC CHARACTERISTICS FOR P80CL31 AND
P80CL51
22 DC CHARACTERISTICS FOR P80C51
23 AC CHARACTERISTICS
24 P85CL000HFZ ‘PIGGY-BACK’
SPECIFICATION
24.1 General description
24.2 Feature differences/additional features with
respect to P80CL51
24.3 Common specification/feature differences
between P85CL000HFZ and
P83CL410/P80CL51
25 PACKAGE OUTLINES
26 SOLDERING
26.1 Introduction
26.2 DIP
26.3 QFP and VSO
27 DEFINITIONS
28 LIFE SUPPORT APPLICATIONS
1997 Apr 15 2
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
1 FEATURES
• Full static 80C51 Central Processing Unit
• 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP,
40-lead VSO or 44-lead QFP package
• 128 bytes on-chip RAM Data Memory
• 4 kbytes on-chip ROM Program Memory for P80CL51
• External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes
• Four 8-bit ports; 32 I/O lines
• Two 16-bit Timer/Event counters
• On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator
• Thirteen source, thirteen vector, nested interrupt
structure with two priority levels
• Full duplex serial port (UART)
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
– four 8-byte RAM register banks
– stack depth limited only by available internal RAM
(maximum 128 bytes)
– multiply, divide, subtract and compare instructions
• Reduced power consumption through Power-down and
Idle modes
• Wake-up via external interrupts at Port 1
• Frequency range: 0 to 16 MHz (P80C51: 3.5 MHz min.)
• Supply voltage: 1.8 to 6.0 V (P80C51: 5.0 V ±10%)
• Very low current consumption
• Operating ambient temperature range: −40 to +85 °C.
P80CL31; P80CL51
2 GENERAL DESCRIPTION
The P80CL31; P80CL51 (hereafter generally referred to
as the P80CLx1) is manufactured in an advanced CMOS
technology. The P80CLx1 has the same instruction set as
the 80C51, consisting of over 100 instructions:
49 one-byte, 46 two-byte, and 16 three-byte. The device
operates over a wide range of supply voltages and has low
power consumption; there are two software selectable
modes for power reduction: Idle and Power-down.
For emulation purposes, the P85CL000 (piggy-back
version) with 256 bytes of RAM is recommended.
This data sheet details the specific properties of the
P80CL31; P80CL51. For details of the 80C51 core see
“Data Handbook IC20”
2.1 Versions: P80CL31 and P80C51
The P80CL31 is the ROMless version of the P80CL51.
The mask options on the P80CL31 are fixed as follows:
• All ports have option ‘1S’ (standard, HIGH after reset)
• Oscillator option: Oscillator 3
• Power-on-reset option: OFF.
The P80C51 is a restricted-voltage range version of the
P80CL51. The operating voltage is 5.0 V ±10%.
3 APPLICATIONS
The P80CLx1 is especially suited for real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.
The P80CLx1 also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities.
.
1997 Apr 15 3
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
P80CL31; P80CL51
UART
4 ORDERING INFORMATION
TYPE NUMBER
ROMless ROM NAME DESCRIPTION VERSION
P80CL31HFP P80CL51HFP DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
P80CL31HFT P80CL51HFT VSO40 plastic very small outline package; 40 leads SOT158-1
P80CL31HFH P80CL51HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
− P80C51HFP DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
− P80C51HFT VSO40 plastic very small outline package; 40 leads SOT158-1
− P80C51HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
Note
1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
(1)
PACKAGE
SOT307-2
body 10 × 10 × 1.75 mm
SOT307-2
body 10 × 10 × 1.75 mm
1997 Apr 15 4
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
5 BLOCK DIAGRAM
counter (1)
T0 T1
TWO 16-BIT
COUNTERS
TIMER/EVENT
SERIAL PORT
PROGRAMMABLE
FULL DUPLEX UART
SYNCHRONOUS SHIFT
P80CL31; P80CL51
MLA556
(1)
RXD TXD
reference
frequency
XTAL2 XTAL1
DATA
MEMORY
(128 x 8 RAM)
MEMORY
PROGRAM
(4K x 8 ROM)
AND
TIMING
OSCILLATOR
P80CL31
P80CL51
CPU
PROGRAMMABLE I/O
CONTROL
EXPANSION
64 kbyte BUS
internal
interrupts
10 3
and I/O pins
address/data bus
Fig.1 Block diagram.
control parallel ports,
external interrupts (1)
1997 Apr 15 5
(1) Pins shared with parallel port pins.
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
6 FUNCTIONAL DIAGRAM
V
handbook, full pagewidth
XTAL1
XTAL2
EA
SS
P80CL31; P80CL51
V
DD
RST
port 0
address and
data bus
alternative
functions
RXD / data
TXD / clock
INT0
INT1
T0
T1
WR
RD
PSEN
port 3
ALE
P80CL31
P80CL51
MLA557
port 1
port 2
INT2/INT9
address bus
Fig.2 Functional diagram.
1997 Apr 15 6
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
7 PINNING INFORMATION
7.1 Pinning
handbook, halfpage
P1.0/INT2
P1.1/INT3
P1.2/INT4
P1.3/INT5
P1.4/INT6
P1.5/INT7
P1.6/INT8
P1.7/INT9
P3.0/RXD/data
P3.0/TXD/clock
P3.2/INT0
RST
1
2
3
4
5
6
7
8
9
10
11
12
P80CL31
P80CL51
40
39
38
37
36
35
34
33
32
31
30
29
V
DD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
P80CL31; P80CL51
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
13
14
15
16
17
18
19
20
MLA558
28
27
26
25
24
23
22
21
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
Fig.3 Pin configuration for DIP40 and VSO40 packages.
1997 Apr 15 7
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
handbook, full pagewidth
P1.1/INT3
P1.2/INT4
P1.3/INT5
P1.4/INT6
44
43
42
41
1P1.5/INT7
RST
n.c.
2
3
4
5
6
7
8
9
10
11
P1.6/INT8
P1.7/INT9
P3.0/RXD/data
P3.1/TXD/clock
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
n.c.
P1.0/INT2
40
39
P80CL31
P83CL51
DD
V
38
P0.1/AD1
P0.0/AD0
37
36
P0.3/AD3
P0.2/AD2
35
34
P80CL31; P80CL51
P0.4/AD4
33
32
P0.5/AD5
31
P0.6/AD6
30
P0.7/AD7
29
EA
n.c.
28
27
ALE
PSEN
26
25
P2.7/A15
24
P2.6/A14
23
P2.5/A13
12
13
14
15
16
SS
P3.7/RD
P3.6/WR
XTAL2
XTAL1
V
Fig.4 Pin configuration for QFP44 package.
1997 Apr 15 8
17
n.c.
18
19
P2.0/A8
P2.1/A9
20
21
P2.2/A10
P2.3/A11
22
MBK034
P2.4/A12
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
P80CL31; P80CL51
UART
7.2 Pin description Table 1 Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages
For more extensive description of the port pins see Chapter 10 “I/O facilities”.
PIN
SYMBOL
INT2 1 40 • Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have
P1.0/
P1.1/
INT3 2 41
INT4 3 42
P1.2/
INT5 4 43
P1.3/
INT6 5 44
P1.4/
INT7 6 1
P1.5/
INT8 7 2
P1.6/
INT9 8 3
P1.7/
RST 9 4 Reset: a HIGH level on this pin for two machine cycles while the oscillator
P3.0/RXD/data 10 5 • Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
P3.1/TXD/clock 11 7
P3.2/INT0 12 8
INT1 13 9
P3.3/
P3.4/T0 14 10
P3.5/T1 15 11
WR 16 12
P3.6/
RD 17 13
P3.7/
XTAL2 18 14 Crystal oscillator output: output of the inverting amplifier of the oscillator.
XTAL1 19 15 Crystal oscillator input: input to the inverting amplifier of the oscillator,
V
SS
P2.0 to P2.7
A8 to A15
PSEN 29 26 Program Store Enable. Output read strobe to external Program Memory.
DIP40
VSO40
20 16 Ground: circuit ground potential.
21 to 28 18 to 25 • Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups.
QFP44
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 1 pins that are externally
pulled LOW will source current (IIL, see Chapter 21) due to the internal
pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.
• Alternative functions:
– INT2 to INT9 are external interrupt inputs.
is running resets the device.
Same characteristics as Port 1.
• Alternative functions:
– RXD/data is the serial port receiver data input (asynchronous) or data
input/output (synchronous)
– TXD/clock is the serial port receiver data output (asynchronous) or
clock output (synchronous)
INT0 and INT1 are external interrupts 0 and 1
–
– T0 and T1 are external inputs for timers 0 and 1
– WR is the external Data Memory write strobe
– RD is the external Data Memory read strobe.
Left open when external clock is used.
also the input for an externally generated clock source.
Same characteristics as Port 1.
• High-order addressing: Port 2 emits the high-order address byte
(A8 to A15) during accesses to external memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory that
use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
When executing code out of external Program Memory ,PSEN is activated
twice each machine cycle. However, during each access to external Data
Memory two PSEN activations are skipped.
DESCRIPTION
1997 Apr 15 9
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
P80CL31; P80CL51
UART
PIN
SYMBOL
ALE 30 27 Address Latch Enable. Output pulse for latching the low byte of the
EA 31 29 External Access. When EA is held HIGH the CPU executes out of internal
P0.7 to P0.0
AD7 to AD0
V
DD
n.c. − 6, 17, 28,39Not connected.
DIP40
VSO40
32 to 39 30 to 37 • Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
40 38 Power supply.
QFP44
address during access to external memory. ALE is emitted at a constant
rate of1⁄6× f
(assuming MOVX instructions are not used).
program memory (unless the program counter exceeds 0FFFH). Holding
EA LOW forces the CPU to execute out of external memory regardless of
the value of the program counter.
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to
them float, and in that state will function as high impedance inputs.
• Low-order addressing: Port 0 is also the multiplexed low-order address
and data bus during access to external memory. The strong internal
pull-ups are used while emitting logic 1s within the low order address.
, and may be used for external timing or clocking purposes
osc
DESCRIPTION
1997 Apr 15 10
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
8 FUNCTIONAL DESCRIPTION OVERVIEW
This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters as follows:
Chapter 9 “Memory organization”
Chapter 10 “I/O facilities”
Chapter 11 “Timers/event counters”
Chapter 12 “Reduced power modes”
Chapter 13 “Standard serial interface SIO0: UART”
Chapter 14 “Interrupt system”
Chapter 15 “Oscillator circuitry”
Chapter 16 “Reset”.
8.1 General
The P80CLx1 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.
P80CL31; P80CL51
The P80CLx1 contains 4 kbytes Program Memory (ROM;
P80CL51 only); a static 128 bytes Data Memory (RAM);
32 I/O lines; two16-bit timer/event counters;
a thirteen-source, two priority-level, nested interrupt
structure and on-chip oscillator and timing circuit.
A standard UART serial interface is also provided.
The device has two software-selectable modes of reduced
activity for power reduction:
• Idle mode; freezes the CPU while allowing the timers,
serial I/O and interrupt system to continue functioning.
• Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
8.2 CPU timing
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1 µs if the oscillator
frequency (f
) is 12 MHz.
osc
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.
1997 Apr 15 11
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
9 MEMORY ORGANIZATION
The P80CLx1 has 4 kbytes of Program Memory (ROM;
P80CL51 only) plus 128 bytes of Data Memory (RAM) on
board.The device has separate address spaces for
Program and Data Memory (see Fig.5). Using Port latches
P0 and P2, the P80CLx1 can address a maximum of
64 kbytes of program memory and a maximum of
64 kbytes of data memory. The CPU generates both read
(RD) and write (WR) signals for external Data Memory
accesses, and the read strobe (PSEN) for external
Program Memory.
9.1 Program Memory
The P80CL51 contains 4 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 4 kbytes of Program Memory can be
implemented in either on-chip ROM or external Program
Memory.
EA pin is tied to VDD, then Program Memory fetches
If the
from addresses 0000H to 0FFFH are directed to the
P80CL31; P80CL51
internal ROM. Fetches from addresses 1000H to FFFFH
are directed to external ROM. Program Counter values
greater than 0FFFH are automatically addressed to
external memory regardless of the state of the
9.2 Data Memory
The P80CLx1 contains 128 bytes of internal RAM and 25
Special Function Registers (SFR). The memory map
(Fig.5) shows the internal Data Memory space divided into
the lower 128, the upper 128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as
mapped in Fig.6. The lowest 32 bytes are grouped into 4
banks of 8 registers. Program instructions refer to these
registers within a register bank as R0 through R7. Two bits
in the Program Status Word select which register bank is
in use. The next 16 bytes above the register banks form a
block of bit-addressable memory space. The 128 bits in
this area can be directly addressed by the single-bit
manipulation instructions. The remaining registers
(30H to 7FH) are directly and indirectly byte addressable.
EA pin.
handbook, full pagewidth
4095
64K
4096
INTERNAL
(EA = 1)
PROGRAM MEMORY
EXTERNAL
4095
EXTERNAL
(EA = 0)
255
127
OVERLAPPED SPACE
INTERNAL
DATA RAM
0
INTERNAL DATA MEMORY
SPECIAL
FUNCTION
REGISTERS
MLA559
64K
0
EXTERNAL
DATA MEMORY
Fig.5 Memory map.
1997 Apr 15 12
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
handbook, halfpage
R7
R0
R7
R0
R7
7FH
30H
2FH
20H
1FH
18H
17H
10H
0FH
P80CL31; P80CL51
bit-addressable space
(bit addresses 0 to 7F)
4 banks of 8 registers
(R0 to R7)
R0
R7
R0
Fig.6 The lower 128 bytes of internal RAM.
9.3 Special Function Registers (SFRs)
The upper 128 bytes are the address locations of the
SFRs. Figure 7 shows the SFR space. The SFRs include
the port latches, timers, peripheral control, serial I/O
registers, etc. These registers can only be accessed by
direct addressing. There are 128 directly addressable
locations in the SFR address space (SFRs with addresses
divisible by eight).
9.4 Addressing
The P8xCL410 has five methods for addressing source
operands:
• Register
• Direct
• Register-indirect
• Immediate
• Base-register plus index-register-indirect.
08H
07H
0
MLA560 - 1
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
Access to memory addressing is as follows:
• Registers in one of the four register banks through
register, direct or register-indirect
• Internal RAM (128 bytes) through direct or
register-indirect
• Special Function Registers through direct
• External data memory through register-indirect
• Program Memory look-up tables through base-register
plus index-register-indirect.
1997 Apr 15 13
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
ook, full pagewidth
REGISTER
MNEMONIC
IP1
IX1
ACC
PSW
IRQ1
IP0
BIT ADDRESS
FEFF FD FC FB FA F9 F8
F6F7 F5 F4 F3 F2 F1 F0 F0HB
EEEF ED EC EB EA E9 E8 E8HIEN1
E6E7 E5 E4 E3 E2 E1 E0
D6D7 D5 D4 D3 D2 D1 D0
C6C7 C5 C4 C3 C2 C1 C0
BD BC BB BA B9 B8
DIRECT
BYTE ADDRESS (HEX)
F8H
E9H
E0H
D0H
C0H
B8H
P80CL31; P80CL51
P3
IEN0
P2
S0BUF
S0CON
P1
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
SP
P0
B5 B4 B3 B2 B1 B0B6B7
AEAF AD AC AB AA A9 A8
A6A7 A5 A4 A3 A2 A1 A0
9E9F 9D 9C 9B 9A 99 98
9697 95 94 93 92 91 90
8E8F 8D 8C 8B 8A 89 88
8687 85 84 83 82 81 80
MLA561
B0H
A8H
A0H
99H
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
SFRs containing
directly addressable
bits
Fig.7 Special Function Register memory map.
1997 Apr 15 14
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
10 I/O FACILITIES
10.1 Ports
The P80CLx1 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the alternative functions
detailed below. To enable a port pin alternate function, the
port bit latch in its SFR must contain a logic 1.
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
Port 1 Provides the inputs for the external interrupts
INT2 to INT9.
Port 2 Provides the high-order address when expanding
the device with external Program or Data Memory.
Port 3 Pins can be configured individually to provide:
• External interrupt request inputs: INT1 and INT0
• Timer/counter inputs: T1 and T0
• Control signals to read and write to external
memories: RD and WR
• UART input and output: RXD/data and
TXD/clock.
Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Ports 1, 2, and 3 have internal
pull-ups Figure 8(a) shows that the strong transistor ‘p1’ is
turned on for only 2 oscillator periods after a LOW-to-HIGH
transition in the port latch. When on, it turns on ‘p3’ (a weak
pull-up) through the inverter. This inverter and ‘p3’ form a
latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is
only on when emitting logic 1s for external memory
access. Writing a logic 1 to a Port 0 bit latch leaves both
output transistors switched off so that the pin can be used
as a high-impedance input.
10.2 Port options
The pins of port 1, port 2 and port 3 may be individually
configured with one of the following options. These options
are also shown in Fig.8.
Option 1 Standard Port; quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned
on for two oscillator periods after a
LOW-to-HIGH transition in the port latch;
Fig.8(a).
P80CL31; P80CL51
Option 3 Push-pull; output with drive capability in both
polarities. Under this option, pins can only be
used as outputs; see Fig.8(c).
10.3 Port 0 options
The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (
boundary) and second, I/O accesses.
10.3.1 E
Option 1 True logic 0 and logic 1 are written as address to
Option 2 An external pull-up resistor is required for
Option 3 Not allowed for external memory accesses as
10.3.2 I/O A
Option 1 When writing a logic 1 to the port latch, the
Option 2 Open-drain; quasi-directional I/O with n-channel
Option 3 Push-Pull; output with drive capability in both
10.4 SET/RESET options
Individual mask selection of the post-reset state is
available with any of the above pins. The required
selection is made by appending ‘S’ or ‘R’ to Options 1, 2,
or 3 above.
Option R RESET, at reset this pin will be initialized LOW.
Option S SET, at reset this pin will be initialized HIGH.
EA = 0 or access above the built-in memory
XTERNAL MEMORY ACCESSES
the external memory (strong pull-up to be used).
external accesses.
the port can only be used as output.
CCESSES
strong pull-up ‘p1’ will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.
open-drain output. Use as an output requires the
connection of an external pull-up resistor.
See Fig.8(b).
polarities. Under this option pins can only be
used as outputs. See Fig.8(c).
Option 2 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.8(b).
1997 Apr 15 15
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
handbook, full pagewidth
from port latch
read port pin
input data
2 oscillator
periods
Q
strong pull-up
INPUT
BUFFER
(a) Standard
P80CL31; P80CL51
+5 V
p2
p1
n
p3
I/O pin
+5 V
from port latch
read port pin
from port latch
Q
input data
Q
n
INPUT
BUFFER
(b) Open-drain
strong pull-up
+5 V
external
pull-up
I/O pin
p1
I/O pin
n
(c) Push-pull
Fig.8 Port configuration options.
1997 Apr 15 16
MGD677
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
11 TIMERS/EVENT COUNTERS
The P80CLx1 contains two16-bit timer/event counter
registers; Timer 0 and Timer 1, which can perform the
following functions:
• Measure time intervals and pulse durations
• Count events
• Generate interrupt requests.
In the ‘Timer’ operating mode the register is incremented
every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is1⁄12× f
In the ‘Counter’ operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
1
rate is
should be held for at least one complete machine cycle.
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
Mode 3 Timer 0 establishes TL0 and TH0 as two
⁄24× f
. To ensure a given level is sampled, it
osc
prescaler.
reload upon overflow.
separate counters.
osc
.
P80CL31; P80CL51
The following functions remain active during the Idle
mode:
• Timer 0 and Timer 1
• UART
• External interrupt.
These functions may generate an interrupt or reset; thus
ending the Idle mode.
There are two ways to terminate the Idle mode:
1. Activation of any enabled interrupt will cause IDL
(PCON.0) to be cleared by hardware thus terminating
the Idle mode. The interrupt is serviced, and following
the RETI instruction, the next instruction to be
executed will be the one following the instruction that
put the device in the Idle mode. The flag bits GF0
(PCON.2) and GF1 (PCON.3) may be used to
determine whether the interrupt was received during
normal execution or during the Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When the Idle
mode is terminated by an interrupt, the service routine
can examine the status of the flag bits.
2. The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.
12 REDUCED POWER MODES
There are two software selectable modes of reduced
activity for further power reduction: Idle and Power-down.
12.1 Idle mode
Idle mode operation permits the external interrupts, UART,
and timer blocks to continue to function while the clock to
the CPU is halted.
Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 2). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated.
Once in Idle mode, the CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 3.
1997 Apr 15 17
12.2 Power-down mode
Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.9.
Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 2).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.
Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and
In the Power-down mode, VDD may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
PSEN are held LOW.
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
12.3 Wake-up from Power-down mode
When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT9,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 12.3.1; 12.3.2 and
illustrated in Fig.10.
12.3.1 W
If any of the interrupts INT2 to INT9 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.
12.3.2 W
To wake-up the P80CLx1, the RST pin must be kept HIGH
for a minimum of 24 periods. The on-chip delay counter is
inactive. The user must ensure that the oscillator is stable
before any operation is attempted.
AKE-UP USING INT2 TO INT9
AKE-UP USING RST
P80CL31; P80CL51
12.4 Power Control Register (PCON)
See Tables 2 and 3. Idle and Power-down modes are
activated by software using this SFR. PCON is not
bit-addressable.
12.5 Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 4. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.8(a).
Table 2 Power Control Register (address 87H)
7 6 543210
SMOD −−−GF1 GF0 PD IDL
Table 3 Description of PCON bits
BIT SYMBOL DESCRIPTION
7 SMOD Double Baud rate bit; see description of UART
6, 5, 4 − reserved
3 and 2 GF1 and GF0 General purpose flag bits
1PDPower-down bit; setting this bit activates the Power-down mode
0 IDL Idle mode bit; setting this bit activates the Idle mode
Table 4 Status of external pins during Idle and Power-down modes
MODE MEMORY ALE
Idle internal 1 1 port data port data port data port data port data
external 1 1 floating port data address port data port data
Power-down internal 0 0 port data port data port data port data port data
external 0 0 floating port data port data port data port data
PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
1997 Apr 15 18
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
handbook, full pagewidth
OSCILLATOR
PD
P80CL31; P80CL51
XTAL1XTAL2
interrupts
serial ports
CLOCK
GENERATOR
timer blocks
CPU
IDL
MLA563
handbook, full pagewidth
power-down
RST pin
external
interrupt
oscillator
Fig.9 Internal clock control in Idle and Power-down mode.
delay counter
1536 periods
24 periods
MGD679
Fig.10 Wake-up operation.
1997 Apr 15 19
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
UART
13 STANDARD SERIAL INTERFACE SIO0: UART
This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. (However, if the first byte has not
been read by the time the reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed via the
Special Function Register S0BUF. Writing to S0BUF loads
the transmit register and reading S0BUF accesses a
physically separate receive register.
The serial port can operate in 4 modes:
Mode 0 Serial data enters and exits through RXD. TXD
outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in Special Function
Register S0CON. The baud rate is variable.
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(logic 1). On transmit, the 9th data bit (TB8 in
S0CON) can be assigned the value of a logic 0 or
logic 1. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the
9th data bit goes into RB8 in S0CON, while the
stop bit is ignored. The baud rate is
programmable to either1⁄32or1⁄64× f
Mode 3 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9th data bit and a
stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.
1
⁄12× f
osc
.
.
osc
P80CL31; P80CL51
In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
13.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
th
bit goes into RB8. The following bit is the stop bit.
The 9
The port can be programmed such that when the stop bit
is received, the serial port interrupt will be activated, but
only if RB8 = 1. This feature is enabled by setting bit SM2
in S0CON. One use of this feature, in multiprocessor
systems, is as follows.
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9
address byte and LOW in a data byte. With SM2 = 1,
no slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each slave
can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and
prepare to receive the data bytes that will be sent. The
slaves that were not being addressed leave their SM2 bits
set and go on about their business, ignoring the coming
data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.
13.2 Serial Port Control and Status Register
(S0CON)
The Serial Port Control and Status Register is the Special
Function Register S0CON. The register contains not only
the mode selection bits, but also the 9
and receive (TB8 and RB8), and the serial port interrupt
bits (TI and RI).
th
bit is HIGH in an
th
data bit for transmit
1997 Apr 15 20
Philips Semiconductors Product specification
Low voltage 8-bit microcontrollers with
P80CL31; P80CL51
UART
Table 5 Serial Port Control Register (address 98H)
76543210
SM0 SM1 SM2 REN TB8 RB8 TI RI
Table 6 Description of S0CON bits
BIT SYMBOL DESCRIPTION
7 SM0 These bits are used to select the serial port mode; see Table 7.
6 SM1
5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if
SM2 = 1, then RI will not be activated if the received 9
In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received.
In Mode 0, SM2 should be a logic 0.
4 REN Enables serial reception and is set by software to enable reception, and cleared by
software to disable reception.
th
3 TB8 Is the 9
data bit that will be transmitted in Modes 2 and 3; set or cleared by software as
desired.
th
2 RB8 In Modes 2 and 3, is the 9
data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop
bit that was received; in Mode 0, RB8 is not used.
1TIThe transmit interrupt flag. Set by hardware at the end of the 8
at the beginning of the stop bit time in the other modes, in any serial transmission. Must
be cleared by software.
0RIThe receive interrupt flag. Set by hardware at the end of the 8
halfway through the stop bit time in the other modes, in any serial transmission (except
see SM2). Must be cleared by software.
th
data bit (RB8) is a logic 0.
th
bit time in Mode 0, or
th
bit time in Mode 0, or
Table 7 Selection of the serial port modes
SM0 SM1 MODE DESCRIPTION BAUD RATE
0 0 Mode 0 Shift register
0 1 Mode 1 8-bit UART variable
1
1 0 Mode 2 9-bit UART
⁄32or1⁄64× f
1 1 Mode 3 9-bit UART variable
1
⁄12× f
osc
osc
1997 Apr 15 21
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