Philips OQ8844 Datasheet

INTEGRATED CIRCUITS
DATA SH EET
OQ8844
Digital Servo Driver (DSD-2)
Product specification File under Integrated Circuits, IC01
1995 Nov 27
Digital Servo Driver (DSD-2) OQ8844
FEATURES Servo functions
1-bit class-D focus actuator driver (3.3 Ω)
1-bit class-D radial actuator driver (3.7 Ω)
1-bit class-D sledge motor driver (2.5 Ω).

GENERAL DESCRIPTION

The OQ8844 or Digital Servo Driver 2 (DSD2) consists of 1-bit class-D power drivers, which are specially designed for digital servo applications. Three such amplifiers are integrated in one chip, to drive the focus and radial actuators and the sledge motor of a compact disc optical system.

Other features

Supply voltage 5 V only
Small package (SOT163-1)
Higher efficiency, compared with conventional drivers,
due to the class-D principle
Built-in digital notch filters for higher efficiency
The main benefits of using this principle are its higher efficiency grade compared to conventional analog power amplifiers, its higher integration level, its differential output and the fact that only a few external components are needed. When using these digital power drivers in a digital servo application, the statement ‘complete digital servo loop’ becomes more realistic.
Enable input for focus and radial driver
Enable input for sledge driver
Differential outputs for all drivers
Separate power supply pins for all drivers.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DDD
V
DD(F)
V
DD(R)
V
DD(S)
I
DDDq
I
DD(F)
I
DD(R)
I
DD(S)
f
i(clk)
P
tot
T
amb
digital supply voltage 4.5 5.5 V supply voltage focus actuator 4.5 5.5 V supply voltage radial actuator 4.5 5.5 V supply voltage sledge actuator 4.5 5.5 V quiescent supply current digital part −−10 µA supply current focus 126 250 mA supply current radial 20 250 mA supply current sledge 150 560 mA input clock frequency 4.2336 5 MHz total power dissipation 110 mW operating ambient temperature 40 +85 °C

ORDERING INFORMATION

TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
OQ8844 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1995 Nov 27 2
Digital Servo Driver (DSD-2) OQ8844

BLOCK DIAGRAM

RAC
FOC
SLC
CLI
EN1 EN2
4
3
2
7 8
9
OQ8844
CONTROL
V
V
V
DD(R)
DDD
613141
DIGITAL
NOTCH FILTER
DIGITAL
NOTCH FILTER
DIGITAL
NOTCH FILTER
5101718
V
SS(R)
SSD
V
DD(F)
V
SS(F)
V
DD(S)
ENDSTAGE
HBRIDGE
ENDSTAGE
HBRIDGE
ENDSTAGE
HBRIDGE
V
SSS
11 12
15 16
19 20
MBG785
RA+ RA
FO+ FO
SL+ SL
Fig.1 Block diagram.
1995 Nov 27 3
Digital Servo Driver (DSD-2) OQ8844

PINNING

SYMBOL PIN DESCRIPTION
V
DD(S)
SLC 2 PDM input for sledge driver FOC 3 PDM input for focus driver RAC 4 PDM input for radial driver V
SSD
V
DDD
CLI 7 clock input EN1 8 enable input 1 EN2 9 enable input 2 V
SS(R)
RA+ 11 radial driver (positive output) RA 12 radial driver (negative output) V
DD(R)
V
DD(F)
FO+ 15 focus driver (positive output) FO 16 focus driver (negative output) V
SS(F)
V
SSS
SL+ 19 sledge driver (positive output) SL 20 sledge driver (negative output)
supply voltage for sledge motor
1
driver
5 digital ground 6 digital supply voltage
10 radial driver ground
13 radial supply voltage 14 focus supply voltage
17 focus ground 18 sledge driver ground
handbook, halfpage
V
V
1
DD(S)
2
SLC
FOC
3
RAC
4
V
5
SSD
V
DDD
CLI EN1 EN2 RA
SS(R)
6 7 8 9
10
OQ8844
MBG784
Fig.2 Pin configuration.
20
SL SL+
19
V
18
SSS
V
17
SS(F)
16
FO
15
FO+ V
14
DD(F)
V
13
DD(R)
12 11
RA+
1995 Nov 27 4
Digital Servo Driver (DSD-2) OQ8844
FUNCTIONAL DESCRIPTION Principle of a class-D digital power driver
Figure 3 shows the block diagram of one of the digital drivers integrated in the DSD2. It consists of a timing block and four CMOS switches. The input signal is a 1-bit Pulse Density Modulated (PDM) signal, the output of the digital servo ICs.
The maximum operating clock frequency of the device is 5 MHz. With the mentioned digital servo ICs, the operating frequency of the digital drivers is 4.2336 MHz (96 × 44.1 kHz). The sampling frequency of the 1-bit code however is 1.0584 MHz, so internally in the DSD2 the clock speed of the switches will be 1.0584 MHz. The higher input clock frequency is used to make non-overlapping pulses to prevent short-circuits between the supply voltages. For the control of the switches, two states can be distinguished. If the 1-bit code contains a logic 1, switches A and D are closed and current will flow in the direction as shown in Fig.4.
If the 1-bit code contains a logic 0, switches B and C are closed and current will flow in the opposite direction, as shown in Fig.5.
This indicates that the difference between the mean number of ones and zeros in the PDM signal determines the direction in which the actuator or motor will rotate.
half the sample frequency of 1.0584 MHz. This results in a high dissipation and the motor does not move.
To improve the efficiency, a digital notch filter is added at the input of the digital drivers. This filters the Idle mode pattern (1010101010 etc.) see Fig.6.
The amplitude transfer as a function of frequency is given in Fig.7.
Figure 7 shows that the filter has a zero on consequentially filtering out the idle pattern (101010). The output of this filter is a three-level code (1.5-bit). For the control of the switches three states (1.5-bit) can be distinguished: the two states as described earlier and a third one. This state is used when an idling pattern is supplied.
Switches C and D are closed (see Fig.8). In this idle mode, no current will flow and thus the efficiency will be improved. This mode is also used to short-circuit the inductive actuator/motor. In this way, high induction voltages are prevented because the current can commutate via the filter and the short-circuit in the switches. All three drivers (radial, focus and sledge) contain a digital notch filter as described. Each driver has its own power supply pins to reduce crosstalk because of the relative high current flowing through the pins.
1
⁄2fs,
If the mean number of ones and zeros is equal (Idle mode) the current through the motor or actuator is alternated between the positive and negative direction at a speed of
1995 Nov 27 5
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