74F164
8-bit serial-in parallel-out shift register
Product specification 1995 Sep 22
INTEGRATED CIRCUITS
IC15 Data Handbook
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
2
1995 Sep 22 853-0348 15794
FEA TURES
•Gated serial data inputs
•Typical shift frequency of 100MHz
•Asynchronous Master Reset
•Buffered clock and data inputs
•Fully synchronous data transfer
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
through one of two inputs (Dsa, Dsb); either input can be used as an
active High enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-High transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master Reset (MR
) input overrides all
other inputs and clears the register asynchronously, forcing all
outputs Low.
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
SF00717
Dsa
Dsb
Q0
Q1
Q2
Q3
GND
V
CC
Q7
Q6
Q5
Q4
MR
CP
TYPE TYPICAL f
max
TYPICAL SUPPL Y
CURRENT (TOTAL)
74F164 100MHz 33mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, T
amb
= 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%, T
amb
= –40°C to +85°C
NUMBER
14-pin plastic DIP 74F164N I74F164N SOT27-1
14-pin plastic SO 74F164D I74F164D SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Dsa, Dsb Data inputs 1.0/1.0 20µA/0.6mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
MR Master reset input (active-Low) 1.0/1.0 20µA/0.6mA
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
Dsa Dsb
Q0
12
V
CC
= Pin 14
GND = Pin 7
Q1 Q3 Q4
Q0 Q1 Q3 Q4
CP
MR
8
9
SF00713
3 4 5 6 10 11 12 13
IEC/IEEE SYMBOL
1
2
SRG8
&
R
C1/→
8
9
1D
SF00714
3
4
5
6
10
11
12
13
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
1995 Sep 22
3
LOGIC DIAGRAM
DQ
RD
Q0
1
Dsa
Dsb
2
CP
MR
3
8
9
V
CC
= Pin 14
GND = Pin 7
DQ
RD
Q1
4
DQ
RD
Q2
5
DQ
RD
Q3
6
DQ
RD
Q4
10
DQ
RD
Q5
11
DQ
RD
Q6
12
DQ
RD
Q7
13
SF00715
CPCPCPCPCPCPCPCP
FUNCTION TABLE
INPUTS OUTPUTS OPERATING MODE
MR CP Dsa Dsb Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L X X X L L L L L L L L Reset (Clear)
H ↑ l l L q0 q1 q2 q3 q4 q5 q6
H ↑ l h L q0 q1 q2 q3 q4 q5 q6 Shift
H ↑ h l L q0 q1 q2 q3 q4 q5 q6
H ↑ h h H q0 q1 q2 q3 q4 q5 q6
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition.
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition.
qn = Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.
X = Don’t care
↑ = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to V
CC
V
I
OUT
Current applied to output in Low output state 40 mA
Commercial Range 0 to +70
°
O erating free-air tem erature range
Industrial Range –40 to +85
T
stg
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level iput voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
Ik
Input clamp current –18 mA
I
OH
High-level output current –1 mA
I
OL
Low-level output current 20 mA
O erating free-air tem erature range