Philips N74F161AN, N74F163AN, N74F163AD, N74F161AD Datasheet

INTEGRATED CIRCUITS

74F160A*, 74F161A, 74F162A*, 74F163A

4-bit binary counter

* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

Product specification

1996 Jan 29

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
4-bit binary counters	74F161A, 74F163A

FEATURES

•Synchronous counting and loading

•Two count enable inputs for n-bit cascading

•Positive edge-triggered clock

•Asynchronous Master Reset (74F161A)

•Synchronous Reset (74F163A)

•High speed synchronous expansion

•Typical count rate of 130MHz

•Industrial range (±40°C to +85°C) available

DESCRIPTION

4-bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered.

The outputs of the counters may be preset to High or Low level. A

Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the D0±D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs.

A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops (Q0 ± Q3) in 74F161A to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74F163A, the clear function is synchronous. A Low level at the Synchronous Reset (SR) input sets all four outputs of the flip-flops (Q0 ± Q3) to Low levels after the next positive-going transition on the clock (CP) input (provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.

	TYPE	TYPICAL	TYPICAL SUPPLY CURRENT
		fMAX	(TOTAL)
	74F161A	130MHz	46mA
	74F163A

ORDERING INFORMATION

		ORDER CODE		DRAWING
	DESCRIPTION
		COMMERCIAL RANGE	INDUSTRIAL RANGE
				NUMBER
		VCC = 5V ±10%, Tamb = 0°C to +70°C	VCC = 5V ±10%, Tamb = ±40°C to +85°C
	16-pin plastic DIP	N74F161AN, N74F163AN	I74F161AN, I74F163AN	SOT38-4
	16-pin plastic SO	N74F161AD, N74F163AD	I74F161AD, I74F163AD	SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS					DESCRIPTION	74F (U.L.) HIGH/LOW	LOAD VALUE HIGH/LOW
D0 ± D3					Data inputs	1.0/1.0	20μA/0.6mA
CEP					Count Enable Parallel input	1.0/1.0	20μA/0.6mA
CET					Count Enable Trickle input	1.0/2.0	20μA/1.2mA
	CP				Clock input (active rising edge)	1.0/1.0	20μA/0.6mA
					Parallel Enable input (active Low)	1.0/2.0	20μA/1.2mA
	PE
					Asynchronous Master Reset input	1.0/1.0	20μA/0.6mA
	MR
					(active Low) for 74F161A
					Synchronous Reset input	1.0/1.0	20μA/0.6mA
	SR
					(active Low) for 74F163A
	TC				Terminal count output	50/33	1.0mA/20mA
Q0 ± Q3					Flip-flop outputs	50/33	1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.

1996 Jan 29

2

853±0347 16300

Philips Semiconductors	Product specification
4-bit binary counters	74F161A, 74F163A

74F161A PIN CONFIGURATION

				MR				1								16			VCC
				CP															TC
								2								15
				D0															Q0
								3								14
				D1															Q1
								4								13
				D2															Q2
								5								12
				D3															Q3
								6								11
			CEP																CET
								7								10
		GND
								8								9				PE
															SF00656
74F161A LOGIC SYMBOL
									3		4		5		6
9				PE					D0		D1		D2			D3
7				CEP
10				CET															TC					15
2				CP
1				MR					Q0		Q1		Q2			Q3
VCC = Pin 16									14		13		12		11
GND = Pin 8																								SF00658
74F161A LOGIC SYMBOL (IEEE/IEC)
		1					R				CTR DIV 16
		9
							M1
		7
							G3
		10
							G4
		2
								C2 /1,3,4+
		3																						14
							1,2 D
		4																						13
	5																							12
	6																							11
																								15
														4 CT=15

74F163A PIN CONFIGURATION

			SR					1								16			VCC
			CP																TC
								2								15
				D0															Q0
								3								14
				D1															Q1
								4								13
				D2															Q2
								5								12
				D3															Q3
								6								11
			CEP																CET
								7								10
		GND
								8								9				PE
															SF00657
74F163A LOGIC SYMBOL
							3				4		5		6
9				PE					D0		D1		D2			D3
7				CEP
10				CET															TC					15
2				CP
1				SR					Q0		Q1		Q2			Q3
VCC = Pin 16							14				13		12		11
GND = Pin 8																								SF00659
74F163A LOGIC SYMBOL (IEEE/IEC)
		1					2R				CTR DIV 16
		9
							M1
		7
							G3
		10
							G4
		2
								C2 /1,3,4+
		3																						14
							1,2 D
		4																						13
	5																							12
	6																							11
																								15
														4 CT=15

SF00660

SF00661

1996 Jan 29

3

Philips Semiconductors	Product specification
4-bit binary counters	74F161A, 74F163A

STATE DIAGRAM					APPLICATIONS
					+VCC
0	1	2	3	4
						PE	D0	D1	D2	D3
15				5
						CEP
						CET		74F163A		TC
14				6	CLOCK	CP
						SR
							Q0	Q1	Q2	Q3
13				7
12	11	10	9	8						SF00665

Figure 1. Maximum count modifying scheme

Terminal count = 6

SF00664

H H = Enable count

or

L L = Disable count

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

CEP

CEP

CEP

CEP

CEP

CET

74F163A

TC

CET

74F163A

TC

CET

74F163A

TC

CET

74F163A

TC

CET

74F163A

TC

CP

CP

CP

CP

CP

SR Q0 Q1 Q2 Q3

SR

Q0 Q1 Q2

Q3

SR

Q0

Q1 Q2

Q3

SR

Q0

Q1 Q2

Q3

SR

Q0

Q1 Q2

Q3

CP

SF00666

Figure 2. Synchronous multistage counting scheme

74F161A MODE SELECT ± FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

CP

CEP

CET

Dn

Qn

TC

MR

PE

L

X

X

X

X

X

L

L

Reset (clear)

H

↑

X

X

l

l

L

L

Parallel load

H

↑

X

X

l

h

H

(1)

H

↑

h

h

h

X

count

(1)

Count

H

X

l

X

h

X

qn

(1)

Hold (do nothing)

H

X

X

l

h

X

qn

L

1996 Jan 29

4

Philips Semiconductors	Product specification
4-bit binary counters	74F161A, 74F163A

74F163A MODE SELECT ± FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

SR

CP

CEP

CET

PE

Dn

Qn

TC

l

↑

X

X

X

X

L

L

Reset (clear)

h

↑

X

X

l

l

L

L

Parallel load

h

↑

X

X

l

h

H

(2)

h

↑

h

h

h

X

count

(2)

Count

h

X

l

X

h

X

qn

(2)

Hold (do nothing)

h

X

X

l

h

X

qn

L

H

=

High voltage level

h

=

High voltage level one setup prior to the Low-to-High clock transition

L

=

Low voltage level

l

=

Low voltage level one setup prior to the Low-to-High clock transition

qn

=

Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition

X

=

Don't care

↑= Low-to-High clock transition

(1)= The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)

(2)= The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)

74F161A LOGIC DIAGRAM

CP	2
MR	1
PE	9
	10
CET
	7
CEP
D0	3
	D	R Q
			14
	CP	Q	Q0
D1	4
	D	R Q
	CP	Q	13
			Q1
D2	5
	D	R Q
	CP	Q	12
			Q2
D3	6
	D	R Q
	CP	Q	11
			Q3
			15
			TC
VCC = Pin 16
GND = Pin 8			SF00662
1996 Jan 29	5