Philips N74F148N, N74F148D Datasheet
INTEGRATED CIRCUITS
74F148
8-input priority encoder
Product specification
IC15 Data Handbook
1990 Mar 01
Philips Semiconductors Product specification
74F1488-input priority encoder
FEA TURES
•Code conversions
•Multi-channel D/A converter
•Decimal-to-BCD converter
•Cascading for priority encoding of “N” bits
•Input enable capability
•Priority encoding-automatic selection of highest priority input line
•Output enable-active Low when all inputs are High
•Group signal output-active when any input is Low
DESCRIPTION
The 74F148 8-input priority encoder accepts data from eight
active-Low inputs and provides a binary representation on the three
active-Low outputs. A priority is assigned to each input so that when
two or more inputs are simultaneously active, the input with the
highest priority is represented on the output, with input line I
the highest priority . A High on the Enable Input (EI
) will force all
outputs to the inactive (High) state and allow new data to settle
without producing erroneous information at the outputs. A Group
Signal (GS
three data outputs. The GS
this indicates when any input is active. The EO
) output and an Enable Output (EO) are provided with the
is active-Low when any input is Low:
is active-Low when
all inputs are High. Using the Enable Output along with the Enable
Input allows priority encoding of N input signals. Both EO
are active-High when the Enable Input is High.
7 having
and GS
PIN CONFIGURATION
1
I4
5
2
I
I
6
3
I
7
4
EI
5
2
A
6
1
A
TYPICAL
TYPE
PROPAGATION
DELAY
74F148 6.0ns 23mA
16
V
CC
EO
15
GS
14
I3
13
I2
12
1
I
11
I0
107
98GND A0
SF00181
TYPICAL
SUPPLY CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
DESCRIPTION
16-pin plastic DIP N74F148N SOT38-4
16-pin plastic SO N74F148D SOT109-1
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
I1 – I7 Priority inputs (active Low) 1.0/2.0 20µA/1.2mA
I0 Priority input (active Low) 1.0/1.0 20µA/0.6mA
EI Enable input (active Low) 1.0/2.0 20µA/1.2mA
EO Enable output (active Low) 50/33 1.0mA/20mA
GS Group select output (active Low) 50/33 1.0mA/20mA
A0 – A2 Address outputs (active Low) 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
March 1, 1990 853–0345 98994
2
Philips Semiconductors Product specification
74F1488-input priority encoder
LOGIC SYMBOL
10 11 12 13 1 2 3 4
I0 I1 I2 I4 I5 I6 I7I3
5EI
VCC = Pin 16
GND = Pin 8
LOGIC DIAGRAM
A0 A1 A2
976
EI
5
IEC/IEEE SYMBOL
10
11
12
13
EO
GS
7
I
4 3 2 1 13 12 11 10
I6I5I4I3I2I1I0
SF00182
15
14
1
2
3
4
5
HPRI/BIN
10/Z10
11/Z11
2/Z12
3/Z13
4/Z14
5/Z15
6/Z16
7/Z17
EN = α/V18
0 α
1 α
2 α
≥ 1
10
11
12
13
14
15
16
17
18
α
9
7
8
15
14
SF00183
V
= Pin 16
CC
GND = Pin 8
March 1, 1990
9
A2
9
A1
9
A0
GS14EO
15
SF00184
3
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