Philips mb2823 DATASHEETS
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with
reset and enable (3-State)
2
August 24, 1993 853–1705 10616
FEATURES
• Two sets of high speed parallel registers
with positive edge-triggered D-type
flip-flops
• Ideal where high speed, light loading, or
increased fan–in are required with MOS
microprocessors
• Live insertation/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The MB2823 dual bus interface register is
designed to eliminate the extra packages
required to buffer existing registers and
provide extra data width for wider
data/address paths of buses carrying parity.
The MB2823 has two 9-bit wide buffered
registers with Clock Enable (nCE
) and
Master Reset (nMR
) which are ideal for parity
bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The
state of each D input, one set–up time before
the Low-to-High clock transition is transferred
to the corresponding flip–flop’s Q output.
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
nCP to nQx
CL = 50pF; VCC = 5V 4.6 ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
OUT
Output capacitance VO = 0V or VCC; 3-state 7 pF
I
CCZ
Total supply current Outputs disabled; VCC = 5.5V 500 nA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
52-Pin Plastic Quad Flat Pack –40°C to +85°C MB2823BB 1418B
PIN CONFIGURATION LOGIC SYMBOL
Vcc
1Q2
1Q1
1Q0
1OE
1MR
1CP
1CE
1D0
GND
1D1
1D2
Vcc
Vcc
2Q6
2Q7
GND
2Q8
2OE
2MR
2CP
2CE
2D8
2D7
2D6
Vcc
19 2220 231716 25 26241514 2118
1Q7
2Q1
1Q8
2Q2
GND
1Q5
2Q4
2Q5
2Q3
1Q4
2Q0
1Q6
1Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
47 4446 434950 41 40425152 4548
1D8
2D2
2D0
GND
1D6
1D5
2D4
2D5
2D3
1D4
2D1
1D7
1D339
38
37
36
35
34
33
32
31
30
29
28
27
MB2823
52-Pin
Quad Flat Pack
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8
46
45
1CP
1CE
47
48
1MR
1OE
44 42 41 39 38 37 36 35 34
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8
49 50 51 1 2 3 5 6 7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8
21
22
2CP
2CE
20
19
2MR
2OE
33 32 31 29 28 27 25 24 23
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
8 9 10 11 12 13 15 16 18
È
È
È
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with
reset and enable (3-State)
August 24, 1993
3
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
48, 19 1OE, 2OE Output enable input (active–Low)
44, 42, 41, 39, 38, 37, 36, 35, 34,
33, 32, 31, 29, 28, 27, 25, 24, 23
1D0-1D8
2D0-2D8
Data inputs
49, 50, 51, 1, 2, 3, 5, 6, 7,
8, 9, 10, 11, 12, 13, 15, 16, 18
1Q0-1Q8
2Q0-2Q8
Data outputs
46, 21 1CP, 2CP Clock pulse input (active rising edge)
45, 22 1CE, 2CE Clock enable input (active–Low)
47, 20 1MR, 2MR Master reset input (active–Low)
4, 17, 30, 43 GND Ground (0V)
14, 26, 40, 52 V
CC
Positive supply voltage
LOGIC DIAGRAM
R Q
nD
nD0
nQ0
nMR
nOE
R Q
nD
nD1
nQ1
R Q
nD
nD2
nQ2
R Q
nD
nD3
nQ3
R Q
nD
nD4
nQ4
R Q
nD
nD5
nQ5
R Q
nD
nD6
nQ6
R Q
nD
nD7
nQ7
R Q
nD
nD8
nQ8
CP CP CP CP CP CP CP CP CP
nCP
nCE
LOGIC SYMBOL (IEEE/IEC)
44 49
42 50
41 51
39 1
38 2
37 3
36 5
35 6
2D
1C2
46
G1
45
13
4
7
R
EN
47
48
33 8
32 9
31 10
29 11
28 12
27 13
25 16
24 16
2D
1C2
21
G1
22
23 18
R
EN
20
19
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with
reset and enable (3-State)
August 24, 1993
4
FUNCTION TABLE
INPUTS OUTPUTS OPERATING MODE
nOE nMR nCE nCP nDx nQ0 – nQ8
L L X X X L Clear
L H L ↑ h H Load and read data
L H L ↑ l L
L H H ↑ X NC Hold
H X X X X Z High impedance
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition
↑
= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current output in Low state 128 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN MAX
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
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