Philips MB2543BB Datasheet

Philips Semiconductors Advanced BiCMOS Products Product specification

MB2543

Dual octal latched transceivers with dual enable
(3-State)

1

August 23, 1993 853–1656 10584

FEATURES

•Two 8-bit octal transceivers with D-type

latch

•Live insertation/extraction permitted

•Power-up 3-State

•Power-up reset

•Multiple V

CC

and GND pins minimize

switching noise

•Back-to-back registers for storage

•Separate controls for data flow in each

direction

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per

Jedec JC40.2 Std 17

•ESD protection exceeds 2000V per MIL

STD 883 Method 3015 and 200V per
Machine Model

DESCRIPTION

The MB2543 high-performance BiCMOS
device combines low static and dynamic

power dissipation with high speed and high
output drive.

The MB2543 dual octal registered transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB

,

nLEBA

) and Output Enable (nOEAB,

nOEBA

) inputs are provided for each
register to permit independent control of data
transfer in either direction. The outputs are
guaranteed to sink 64mA.

QUICK REFERENCE DATA

SYMBOL PARAMETER

CONDITIONS

T

amb

= 25°C; GND = 0V

TYPICAL UNIT

t

PLH

t

PHL

Propagation delay
nAx to nBx

CL = 50pF; VCC = 5V 3.3 ns

C

IN

Input capacitance VI = 0V or V

CC

4 pF

C

I/O

I/O capacitance VO = 0V or V

CC;

3-State 7 pF

I

CCZ

Total supply current Outputs disabled; VCC = 5.5V 120 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

52-pin plastic Quad Flat Pack –40°C to +85°C MB2543BB 1418B

PIN CONFIGURATION LOGIC SYMBOL

Vcc

19 2220 231716 25 26241514 2118

2A6

2A7

GND

2EAB

2LEAB

2OEAB

2OEBA

2LEBA

2EBA

2B7

2B6

Vcc

Vcc

1A2
1A3
1A4

GND

1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5

1
2

3
4

5
6

7
8

9
10
11
12
13

47 4446 434950 41 40425152 4548

1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
GND
2B3
2B4
2B5

39
38
37
36

35
34

33
32

31
30
29
28
27

MB2543

52-pin PQFP

1A1

1A0

1EAB

1LEAB

1OEAB

1OEBA

1LEBA

1EBA

GND

1B0

1B1

Vcc

42 41 39 38 37 36 35 34

1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7

50 51 1 2 3 5 6 7

1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7

49
44

1EAB

1EBA
48 1LEAB
45 1LEBA

471OEAB
461OEBA

33 32 31 29 28 27 25 24

2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7

8 9 10 11 12 13 15 16

2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
18

23

2EAB

2EBA
19 2LEAB
22 2LEBA

202OEAB
212OEBA

Philips Semiconductors Advanced BiCMOS Products Product specification

MB2543

Dual octal latched transceivers with dual enable
(3-State)

August 23, 1993

2

LOGIC DIAGRAM

D

LE

Q

D

LE

Q

DETAIL A

nB0

nB1nA1
nB2nA2
nB3nA3
nB4nA4
nB5nA5
nB6nA6
nB7nA7

DETAIL A X 7

nOEAB

nEAB

nLEAB

nOEBA

nEBA

nLEBA

nA0

LOGIC SYMBOL (IEEE/IEC)

42

41

39

38

37

36

35

34

&

&

&
&

50

51

1

2

3

5

6

7

47
49
48
46
44
45

EN1(AB)

EN2(BA)

∇ 1

&

&

&
&

8

9

10

11

12

13

15

16

20
18
19
21
23
22

EN1(AB)

EN2(BA)

33

32

31

29

28

27

25

24

∇ 1 2 ∇2 ∇

Philips Semiconductors Advanced BiCMOS Products Product specification

MB2543

Dual octal latched transceivers with dual enable
(3-State)

August 23, 1993

3

FUNCTIONAL DESCRIPTION

The MB2543 contains two sets of eight
D-type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB

)

input and the A-to-B Latch Enable (nLEAB

)

input are Low the A-to-B path is transparent.

A subsequent Low-to-High transition of the
nLEAB

signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB

and

nOEAB

both Low, the 3-State B output

buffers are active and display the data
present at the outputs of the A latches.

Control of data flow from B to A is similar, but
using the nEBA

, nLEBA, and nOEBA inputs.

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

50, 51, 1, 2, 3, 5, 6, 7,

8, 9, 10, 11, 12, 13, 15, 16

1A0 – 1A7,

2A0 – 2A7

Data inputs/outputs

42, 41, 39, 38, 37, 36, 35, 34,

33, 32, 31, 29, 28, 27, 25, 24

1B0 – 1B7,

2B0 – 2B7

Data inputs/outputs

47, 46, 20, 21

1OEAB, 1OEBA,

2OEAB

, 2OEBA

A to B / B to A Output Enable inputs (active-Low)

49, 44, 18, 23

1EAB, 1EBA,
2EAB

, 2EBA

A to B / B to A Enable inputs (active-Low)

48, 45, 19, 22

1LEAB, 1LEBA,

2LEAB

, 2LEBA

A to B / B to A Latch Enable inputs (active-Low)

4, 17, 30, 43 GND Ground (0V)

14, 26, 40, 52 V

CC

Positive supply voltage

FUNCTION TABLE

INPUTS OUTPUTS STATUS

nOEXX nEXX nLEXX nAx or nBx nBx or nAx

H X X X Z Disabled
X H X X Z Disabled
L

L

↑
↑

L
L

h

l

Z
Z

Disabled + Latch

L
L

L
L

↑
↑

h

l

H
L

Latch + Display

L
L

L
L

L
L

H

L

H
L

Transparent

L L H X NC Hold

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High transition of nLEXX

or nEXX (XX = AB or BA)
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High transition of nLEXX

or nEXX (XX = AB or BA)
X = Don’t care
↑ = Low-to-High transition of nLEXX

or nEXX (XX = AB or BA)
NC= No change
Z = High impedance or “off” state

Philips Semiconductors Advanced BiCMOS Products Product specification

MB2543

Dual octal latched transceivers with dual enable
(3-State)

August 23, 1993

4

ABSOLUTE MAXIMUM RATINGS

1 , 2

SYMBOL

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +7.0 V

I

IK

DC input diode current VI < 0 –18 mA

V

I

DC input voltage

3

–1.2 to +7.0 V

I

OK

DC output diode current VO < 0 –50 mA

V

OUT

DC output voltage

3

output in Off or High state –0.5 to +5.5 V

I

OUT

DC output current output in Low state 128 mA

T

stg

Storage temperature range –65 to 150 °C

NOTES:

1 . Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

2 . The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3 . The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

V

CC

DC supply voltage 4.5 5.5 V

V

I

Input voltage 0 V

CC

V

V

IH

High-level input voltage 2.0 V

V

IL

Low-level Input voltage 0.8 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 64 mA

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

Operating free-air temperature range –40 +85 °C