Philips LC4.7, FM242(FTV2.1), FTP1.1, FTP2.2 Schematic

Colour Television Chassis

LC 4.7, FM 242 (FTV2.1), FTP 1.1, FTP 2.2 X

Supplement SDI PDP Repair Manual

Contents Page

1 Technical Specifications 2 2 Safety Instructions, Warnings and Notes 6 3 Directions for Use 8 4 Mechanical Instructions 9 5 Diagnostic Software 16 6 Block Diagrams 7 Circuit Diagrams and PWB Layouts 8 Alignments 34 9 Circuit Descriptions 44 10 Spare Parts List 45

Copyright 2004 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

27 33

Published by MW Service PaCE Printed in the Netherlands Subject to modification EN 3122 785 14990

EN 2 S/SD/HD 3.1 PDP1.

Technical Specifications

1. Technical Specifications

1.1 Model / Chassis overview

PDP Type Model Name H x V Pixel Chassis

37”SDv4 S37SD-YD02 (*)

S37SD-YB01

42”SDv2 S42SD-YD06 (*)

S42SD-YB04

42”SDv3 S42SD-YD05 (*)

S42SD-YB03

42”HDv3 S42AX-XD03 (*)

S42AX-XB01

50HDv3 S50HW-XD03 (*)

S50HW-XB02

(*) are Model names with PSU, but only PDP model without PSU will be delivered as spare part

852 x 480 LC4.7

852 x 480 FM242

852 x 480 LC4.7

1024 x 768 FTP2.2U

1366 x 768 FTP2.2E

42" SDv2

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Serial number Model label Voltage label

42" SDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Serial number label Model label Voltage label

(FTV2.1)

FTP1.1

FTP2.2x

Figure 1-2

Points of Screw Mount

Figure 1-1

Figure 1-3

Technical Specifications

EN 3S/SD/HD 3.1 PDP 1.

42"HDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Serial number label Panel model labelVoltage label

Figure 1-4

Points of Screw Mount

Figure 1-7

50" HDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Serial Number

Voltage

label

Panel module label

Figure 1-5

37" SDv4

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU ‘

Voltage label Serial number label Panel module label

Figure 1-8

Points of Screw Mount

Figure 1-9

Figure 1-6

EN 4 S/SD/HD 3.1 PDP1.

Technical Specifications

1.2 Serial Number

2 6 1 4 0 8 07 0 8 6 5

Serial No : 0001~9999 Date : 01~31 Month : 01~12 Year : 00(2000)

Line No : 1 ~ 9 (0:Pilot Line) Type : 02~48

~99(2099)

(ex.50HDv3:26)

(Step of even)

Figure 1-10

1.3 Specifications

No Item Specification 37” SDV4 Specification 42” SDV2 (ypo6)

1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells) 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)

2 Number of Cells 2556 (H) x 480 (V) 2556 (H) x 480 (V)

3 Pixel Pitch 0.960 (H) mm x 0.960 (V) mm 1.095 (H) mm x 1.110 (V) mm

4 Cell Pitch R 0.320 (H) mm x 0.960 (V) mm R 0.324 (H) mm x 1.110 (V) mm

G 0.320 (H) mm x 0.960 (V) mm G 0.365 (H) mm x 1.110 (V) mm

B 0.320 (H) mm x 0.960 (V) mm B 0.406 (H) mm x 1.110 (V) mm

5 Display size

Horizontal 817.92mm x Vertical 460.80mm[ 32.30 inch

x 18.14 inch ]

6 Screen size Diagonal 37" Color Plasma Display Module Diagonal 42" Color Plasma Display Module

7 Screen aspect 16 : 9 16 : 9

8 Display color 16.77 million colors 16.77 million colors

9 Viewing angle

Over 160×(Angle with 50% and greater brightness per-

pendicular to PDP module)

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm 982 (W) x 582 (H) x 52.9 (D) mm

11 Weight Module 1 About 15.5 kg Module 1 About 16.6 kg

Broadcasting reception-

Vertical frequencyand-

PL42SD003C 60Hz/ 50Hz, LVDS PL42SD003C 60Hz/ 50Hz, LVDS

Video/Logic Interface

932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98 inch ]

Over 160×(Angle with 50% and greater brightness per-

pendicular to PDP module)

No Item Specification 42” SDV3

1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)

2 Number of Cells 2556 (H) x 480 (V)

3 Pixel Pitch 1.095 (H) mm x 1.110 (V) mm

4 Cell Pitch R 0.365 (H) mm x 1.110 (V) mm

G 0.365 (H) mm x 1.110 (V) mm

B 0.365 (H) mm x 1.110 (V) mm

5 Display size

932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98 inch ]

6 Screen size Diagonal 42" Color Plasma Display Module

7 Screen aspect 16 : 9

8 Display color 16.77 million colors

9 Viewing angle

Over 160×(Angle with 50% and greater brightness per-

pendicular to PDP module)

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm

11 Weight Module 1 About 16.6 kg

Broadcasting reception-

Vertical frequencyand-

PL42SD003C 60Hz/ 50Hz, LVDS

Video/Logic Interface

Technical Specifications

No Item Specification 42” HDV3 Specification 50” HDV3

1 Pixel

2 Number of Cells 3072 (H) x 768 (V) Horizontal 4,098 x Vertical 768 cells

3 Pixel Pitch Horizontal 912mm x Vertical 693mm Horizontal 810mm x mmVertical 810mm

4 Cell Pitch R Horizontal 0.304mm x Vertical 693mm R Horizontal 270mm x Vertical 810mm

5 Display size

6 Screen size Diagonal 42" Color Plasma Display Module Diagonal 50" Color Plasma Display Module

7 Screen aspect 16 : 9 16 : 9

8 Display color 16.77 million colors 16.77 million colors

9 Viewing angle

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm 1184(W) x 700 (H) x 60.1 (D) mm

11 Weight Module 1 About 18.0 kg Module 1 About 18.0 kg

Broadcasting reception-

Vertical frequencyand-

Video/Logic Interface

Horizontal 1.024 xVertical 768 pixels(1 pixel = 1 R,G,B

cells)

G Horizontal 0.304mm x Vertical 693mm G Horizontal 270mm x Vertical 810mm

B Horizontal 0.304mm x Vertical 693mm B Horizontal 270mm x Vertical 810mm

932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98 inch ]

Over 160×(Angle with 50% and greater brightness per-

pendicular to PDP module)

PL42SD003C 60Hz/ 50Hz, LVDS PL42SD003C 60Hz/ 50Hz, LVDS

Horizontal 1366 x Vertical 768 pixels(1 pixel = 1 R,G,B

cells)

Horizontal 1106.46mm x Vertical 622.08mm

Over 160×(Angle with 50% and greater brightness per-

pendicular to PDP module)

EN 5S/SD/HD 3.1 PDP 1.

EN 6 S/SD/HD 3.1 PDP2.

Safety Instructions, Warnings and Notes

2. Safety Instructions, Warnings and Notes

** To prevent the risks of unit damage, electrical shock and radiation, take the following safety, service, and ESD precautions.

2.1 Safety instructions 

It is not allowed to operate the FTV-set without glass plate. One function of this glass plate is to absorb Infrared Radiation. Without this glass plate the level of Infrared Radiation produced by the plasma display could damage your eyes.

1. Safety regulations require that during a repair: – the set should be connected to the mains via an

isolating transformer ( in this particular case a transformer of

– safety components, indicated by the symbol 

should be replaced by components identical to the original ones;

2. Safety regulations require that after a repair the set must be returned in its original condition. In particular attention should be paid to the following points. – Note: The wire trees should be routed correctly and

fixed with the mounted cable clamps.

– The insulation of the mains lead should be checked for

external damage.

– The electrical DC resistance between the mains plug

and the secondary side should be checked (only for sets that have mains isolated power supply). This check can be done as follows:

– unplug the mains cord and connect a wire between the

two pins of the mains plug;

– set the mains switch to the on position (keep the mains

cord unplugged!);

– measure the resistance value between the pins of the

mains plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 M

– switch off the TV and remove the wire between the two

pins of the mains plug.

– The cabinet should be checked for defects to avoid

touching of any inner parts by the customer.

≥ 800 VA);

Ω and 12 MΩ;

2.2 Warnings

1. ESD  All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD during repair can reduce life drastically. When repairing, make sure that you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.

2. Available ESD protection equipment: – complete kit ESD3 (combining all 6 prior products -

small table mat) 4822 310 10671

– wristband tester 4822 344 13999

3. Never replace modules or other components while the unit is switched on.

4. When making settings, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

). Careless handling

• PDP module has a lot of electric devices. Service engineer must wear equipment(for example, earth ring) to prevent electric shock and working clothes to prevent electrostatic.

• PDP module use a fine pitch connector which is only working by exactly connecting with flat cable. Operator must pay attention to a complete connection when connector is reconnected after repairing.

• The capacitor’s remaining voltage in the PDP module’s circuit board temporarily remains after power is off. Operator must wait for discharging of remaining voltage during at least 1 minute.

2.4 Safety Precautions for Service (Handling, prevention of a electrical shock)

2.4.1 (Safety Precautions)

• Before replacing a board, discharge forcibly

• The remaining electricity from board.

• When connecting FFC and TCPs to the module, recheck

that they are perfectly connected.

• To prevent electrical shock, be careful not to touch leads

during circuit operations.

• To prevent the Logic circuit from being damaged due to

wrong working, do not connect/disconnect signal cables during circuit operations.

• Do thoroughly adjustment of a voltage label and voltage-

insulation.

• Before reinstalling the chassis and the chassis assembly,

be sure to use all protective stuffs including a nonmetal controlling handle and the covering of partitioning type.

• Caution for design change : Do not install any additional

devices to the module, and do not change the electrical circuit design.

• For example: Do not insert a subsidiary audio or video

connector. If you insert It, It cause danger on safety. And, If you change the design or insert, Manufactor guarantee will be not effect. .

• If any parts of wire is overheats of damaged, replace it with

a new specified one immediately, and identify the cause of the problem and remove the possible dangerous factors.

• Examine carefully the cable status if it is twisted or

damaged or displaced. Do not change the space between parts and circuit board. Check the cord of AC power preparing damage.

• Product Safety Mark: Some of electric or implement

material have special characteristics invisible that was related on safety. In case of the parts are changed with new one, even though the Voltage and Watt is higher than before, the Safety and Protection function will be lost.

• The AC power always should be turned off, before next

repair..

• Check assembly condition of screw, parts and wire

arrangement after repairing. Check whether the material around the parts get damaged.

2.3 Handling Precautions for Plasma Display

• PDP module use high voltage that is dangerous to human. Before operating PDP, always check the dust to prevent short circuit. Be careful touching the circuit device when power is on.

• PDP module is sensitive to dust and humidity. Therefore, assembling and disassembling must be done in no dust place.

2.4.2 (Precaution when repairing ESD)

• There is ESD which is easily damaged by electrostatics.(for example Integrated circuit, FET) Electrostatic damage rate of product will be reduced by the following technics

• Before handling semiconductor parts/assembly, must remove positive electric by ground connection, or must wear the antistatic wrist-belt and ring. (It must be operated after removing dust on it - It comes under precaution of electric shock.)

Safety Instructions, Warnings and Notes

EN 7S/SD/HD 3.1 PDP 2.

• After removing ESD assembly, put on it with aluminum stuff on the conductive surface to prevent charging.

• Do not use chemical stuff using Freon. It generates positive electric that can damage ESD.

• Must use a soldering device for ground-tip when soldering or de-soldering ESD.

• Must use anti-static solder removal device. Most removal device do not have antistatic which can charge a enough positive electric enough damaging ESD.

• Before removeing the protective material from the lead of a new ESD, bring the protective material into contact with the chassis or assembly that the ESD is to be installed on.

• When handing an unpacked ESD for replacement, do not move around too much. Moving (legs on the carpet, for example) generates enough electrostatic to damage the ESD.

• Do not take a new ESD from the protective case until the ESD is ready to be installed. Most ESD have a lead, which is easily short-circuited by conductive materials (such as conductive foam and aluminum)

2.5 Notes

A glass plate is positioned before the plasma display. This glass plate can be cleaned with a slightly humid cloth. If due to circumstances there is some dirt between the glass plate and the plasma display panel it is recommended to do some maintenance by a qualified service employee only.

• Routing of the wires and fixing them in position must be done in accordance with the original routing and fixing configuration when servicing is completed. All the wires are routed far away from the areas that become hot (such as the heat sink). These wires are fixed in position with the wire clamps so that the wires do not move, thereby ensuring that they are not damaged and their materials do not deteriorate over long periods of time. Therefore, route the cables and fix the cables to the original position and states using the wire clamps.

• Perform a safety check when servicing is completed. Verify that the peripherals of the serviced points have not undergone any deterioration during servicing. Also verify that the screws, parts and cables removed for servicing purposes have all been returned to their proper locations in accordance with the original

2.5.1 Notes on safe handling of the plasma display

Notes to follow during service

• The work procedures shown with the Note indication are important for ensuring the safety of the product and the servicing work. Be sure to follow these instructions.

• Before starting the work, secure a sufficient working space.

• At all times other than when adjusting and checking the product, be sure to turn OFF the main POWER switch and disconnect the power cable from the power source of the display (jig or the display itself) during servicing.

• To prevent electric shock and breakage of pwb, start the servicing work at least 30 seconds after the main power bas been turned off. Especially when installing and removing the power supply pwb and the SUS pwb in which high voltages are applied, start servicing at least 2 minutes after the main power bas been turned off.

• While the main power is on, do not touch any parts or circuits other than the ones specified. The high voltage power supply block within the PDP module has a floating ground. If any connection other than the one specified is made between the measuring equipment and the high voltage power supply block, it can result in electric shock or activation of the leakage-detection circuit breaker.

• When installing the PDP module in, and removing it from the packing carton, be sure to have at least two persons

• perform the work white being careful to ensure that the flexible printed-circuit cable of the PDP module does not

• get caught by the packing carton.

• When the surface of the panel comes into contact with the cushioning materials, be sure to confirm that there is no foreign matter on top of the cushioning materials before the surface of the panel comes into contact with the cushioning materials. Failure to observe this precaution may result in, the surface of the panel being scratched by foreign matter.

• When handling the circuit pwb, be sure to remove static electricity from your body before handling the circuit pwb.

• Be sure to handle the circuit pwb by holding the large parts as the heat sink or transformer. Failure to observe this precaution may result in the occurrence of an abnormality in the soldered areas.

• Do not stack the circuit pwb. Failure to observe this precaution may result in problems resulting from scratches on the parts, the deformation of parts, and short-circuits due to residual electric charge.

EN 8 S/SD/HD 3.1 PDP3.

3. Directions For Use

Not applicable

Directions For Use

Mechanical Instruction

4. Mechanical Instruction

4.1 Disassembling / Re-asssembling

4.1.1 Disassembling & Re-assembling of FPC (Flexible Printed Circuit) and Y-Buffer (Upper and Lower)

1. Removal procedure

• Pull out the FPC from Connector by holding the lead of the FPC with both hands.

2. Assembling procedures

EN 9S/SD/HD 3.1 PDP 4.

• Push the lead of FPC with same force on both sides into the connector.

Notice: Be careful do not get a damage on the connector pin during connecting by mistake.

4.1.2 Assembling & Disassembling of Flat Cable Connector of X-main Board

1. Disassembling Procedure

• Pull out the clamp of connector.

• Pull Flat cable out press down lightly.

• Turn the Flat cable reversely.

EN 10 S/SD/HD 3.1 PDP4.

2. Assembling Procedures

• Put the Flat cable into the connector press down lightly until locking sound (“Click.“) comes out.

4.1.3 Assembling & Disassembling the FFC and TCP form Connector

1. Disassembling of TCP

Mechanical Instruction

• Open the clamp carefully. • Pull the TCP out from connector.

2. Assembling of TCP

• Put the TCP into the Connector carefully

• Close the clamp completely. (The sound “Click.” comes out.)

Notice:

• 1) Checking whether the foreign material is on the Connector inside before assembling of TCP.

• 2) Be careful do not get a damage on the board by ESD during handling of TCP.

3. Misassembling of TCP

• The misassembling of TCP is the cause of defect.

4. Assembling & Disassembling of FFC

The procedure of assembling and disassembling of FFC is same as TCP

Mechanical Instruction

EN 11S/SD/HD 3.1 PDP 4.

• This is the photo of the assembling of FFC.

4.1.4Exchange of LBE, LBF, LBG board

Photo 1

EN 12 S/SD/HD 3.1 PDP4.

Photo 2 - 42" SDv2

Mechanical Instruction

4617532

Photo 2 - 42" SDv3

4617532

Photo 2 - 42" HDv3

XYG Z[G \G]G ^_

Mechanical Instruction

EN 13S/SD/HD 3.1 PDP 4.

Photo 2 - S37" SDv4

`XW XXXY X[G X\X] XZ

EN 14 S/SD/HD 3.1 PDP4.

Photo 2 - 50" HDv3

Mechanical Instruction

1. 42" SDv3 - Remove the screws in order of 2-3-5-7-1-4-6 and 10-11-13-16-9-12-14 for HD from heat sink and then get rid of heat sink. (Photo 1) 42" HDv3, S37" SDv4, 50" HDv3

- Remove the screws in order of Center - Left Side - Right Side from heat sink and then get rid of heat sink. (Photo 1)

2. Remove the TPC, FFC and power cable from the connectors.

3. Remove all the screws from defected board.

4. Remove the defected board.

5. Replace the new board and then screw tightly.

6. Get rid of the foreign material from the connector.

7. Connect the TCP, FFC and power cable to the connector.

8. Reassemble the TCP heat sink.

9. 42" SDv3 - Screw in order of 4-1-7-6-5-3-2 and 12-9-15-1413-11-10 for HD. (Photo 2) 42" HDv3, S37" SDv4, 50" HDv3

- Screw in order of Right Side - Left Side - Center (Photo 2)

If you screw too tightly, it is possible to get damage on the Driver IC of TCP.

4.1.5 Exchange YBU, YBL and YM board

1. Separate all the FPC connector of YBU (Y-Buffer upper) and YBL (Lower). (Photo 1)

2. Separate all the connector of CN5001 and CN5008 from YMain.

3. Loosen all the screws of YBU, YBL and YM.

4. Remove the board from chassis.

5. Remove the connector of CN5006 and CN5007 among YBU, YBL and YM.

6. Remove the YBL and YBU from Y-main.

7. Replace the defected board.

Mechanical Instruction

EN 15S/SD/HD 3.1 PDP 4.

8. Reassemble the YBU and YBL to the Y-Main.

9. Connect the connector of CN5006 and CN5007 among YBU, YBL and YM.

10. Arrange the board on the chassis and then screw to fix.

11. Connect the FPC and YM of panel to the connector.

12. Supply the electric power to the module and then check the waveform of board.

13. Turn off the power after the waveform is adjusted.

EN 16 S/SD/HD 3.1 PDP5.

5. Diagnostic software

5.1 Repair tools

Diagnostic software

1.) 3122 785 90581 = Foam buffers

2.) Compair connector:

3.) V2 jig 3122 785 90760

4.) V3 jig 3122 785 90770

Figure 5-1 Foam buffers for PDP

3122 785 90800

3122 785 90760

Figure 5-2 3122 785 90760

Figure 5-3 3122 785 90770

5.2 Repair Scenario

Diagnostic software

Repair Scenario FTV with SDI PDP

First check complete set

Fault Symptom?

EN 17S/SD/HD 3.1 PDP 5.

Repair Philips application

Scavio = FM242

SSB EMG = FTP1.1

SSB EMG 2004 = FTP2.2 with LVDS Tool

Power Supply

is working ?

Check if LVDS from SCAVIO

or SSB board is OK

Use LVDS Tool when possible

Output of SSB / SCAVIO

is OK?

SDI repair Scenario

Fault finding; Display fault

Set Type ?

Power supply is not working

No voltage output

Go to Power Supply Check

& repair scenario

With Philips application

or PDP as stand alone check

42FD9925/01

42FD9935/17/93S

42FD9945/01/12/69/79/98

42FD9953/17/69C/69S/93S

42FD9936/37

FM242

Repair Scenario 42SDV2

42PF9945

FTP1.1

37PF9946/12 37PF9936/37

SD SD

LC4.7

Repair Scenario SDV4

42PF9966/37/

79/93/98

42PF9976/37

FTP2.2

Figure 5-4

42PF9936D/37

42PF9946/12/79/93/98

42PF9956/12/93

FTP2..2

LC4.7

Repair Scenario SDV3

50PF9956/37

50PF9966/12/37/69/

50PF9986/37

FTP2..2

EN 18 S/SD/HD 3.1 PDP5.

Diagnostic software

No Voltage output

On/Off relay

RLY8001/8002 acts?

Green LED´s

8001, 8002

are on?

Power Supply Check for 42SDV2

Operating voltages don´t exist V2 Versions

Switch on On/Off switch (vacation switch)

Ye s

Connect set to mains.

LED8003

Stby is on?

Ye s

Switch on via 1 or 2

Check Protection Red

SMPS shutsdown?

Red LED8004 is on.

Protection

LED8004

Check F8002

Fuse 250V/8A

Check CN8004 / 2pin

connector 220V AC

Stanby supply is defective.

Replace PSU

Switch from standby to on; 1 Via RC when Philips application is in. 2 Via Switch on Jig connector when Philips application is removed

Green LED 8001,

8002

& Red LED are off

Blinking

Check Power supply

on Logic-Main board.

Data communication

from Philips

application to Logic

mains is OK.

Call SAM

or SDM

LED on Logic main board ?

Off

3,3V and 5V

Continous on, means no data communication over

LVDS Cable.

Reconnect mains. Switch on via 1 or 2

Ye s

Disconnect mains cord

Disconnect Y-main CN8008

SMPS is working? Disconnect mains cord

Disconnect X-main CN8007

Reconnect mains. Switch on via 1 or 2

SMPS is

Ye s

working?

Check Stanby Line pin 11

on CN8002 must be low.

No switch on of PSU

Go to repair scenario

as stand-alone

Disconnect mains

Disconnect VA Logic Buffer

CN8010 / CN8011

Check SMPS outputs Vs, Va, Vset, Ve, Vsc

see Sticker

If Power supply on Logic

mains is not OK, change PSU

or Logic main board

Go to repair scenario

as stand-alone

Discharge capacitors on Power supply, before

reconnecting X, Y or Logic Buffer board, use

Replace

Y-Main board

2K4/10W discharge resistor

Figure 5-5

Ye s

Replace

X-Main board

Reconnect mains. Switch on via 1 or 2

SMPS is working?

Ye s

Replace defective

Logic Buffer board

Replace PSU

Diagnostic software

EN 19S/SD/HD 3.1 PDP 5.

No Voltage output

On/Off relay

RLY8001/8002 acts?

Green LED´s

8001, 8002

are on?

Power Supply Check for SDV3

Operating voltages don´t exist V3 Versions

Connect set to mains.

LED8003

Stby is on?

Ye s

Switch on via 1 or 2

Check Protection Red

SMPS shutsdown?

Ye s

Red LED8004 is on.

Protection

LED8004

Check CN8001 / 2pin connector 220V AC

Check Fuse F800 / F8002 / F8003

Stanby supply is defective.

Replace PSU

Switch from standby to on; 1 Via RC when Philips application is in. 2 Via Switch on Jig connector when Philips application is removed

Green LED 8001,

8002

& Red LED are off

LEDs 3,3V and 5V

Off

Check Power

supply on Logic-

Main board..

Data communication from

Philips application to Logic

mains is OK.

Call SAM

Check SMPS outputs Vs, Va, Vset, Ve, Vsc

see Sticker

on Logic main board?

Data LED on Logic Main ?

Blinking

or SDM

Continous on, means no data communication over

LVDS Cable.

Go to repair

scenario

as stand-alone

Discharge capacitors on Power supply, before reconnecting X, Y or Logic Buffer board, use 2K4/10W discharge resistor

Ye s

Disconnect mains cord

Disconnect Y-main CN8003

Reconnect mains. Switch on via 1 or 2

Disconnect mains cord SMPS is working?

Disconnect X-main CN8002

Reconnect mains. Switch on via 1 or 2

Ye s

SMPS is working?

Replace

Y-Main board

Replace

X-Main board

Ye s

Check Stanby Line pin 13

on CN8004 must be low.

No switch on of PSU

Go to repair scenario

as stand-alone

Disconnect mains

Disconnect VA Logic Buffer

CN8005 / CN800x

Reconnect mains. Switch on 1 or 2

SMPS is

working?

Ye s

Replace defective

Logic Buffer board

Replace PSU

Figure 5-6

EN 20 S/SD/HD 3.1 PDP5.

Diagnostic software

Repair Scenario SDI PDP panels as stand alone V2 versions

Repair 42SDV2

Check PDP Type number

PDP identification =

S42SD-YD06 S42SD-YD05

For FM242 disconnect and remove SCAVIO Board

For FTP1.1 disconnect and remove SSB and Audio Board

Connect Jig connector to CN8002 (13 pins)

Short circuit between pin 1 & 2 = On/Off switch (vacation switch)

Switch between pin 8 & 11 standby line switch

Short the Jumper J8002

Set the DIP Switch 2 on

the Logic main board to Off

Plug in the Power cord

Go to V3 or V4 repair scenario

3122 785 90760

Go to fault finding part

No Display Abnormal Display

Green Stby LED

8003 is on ?

Ye s

Switch Jig connector switch on

Green LED 8001

& 8002 are on?

Ye s

Some horizontal or

Vertical Lines don´t exist

Figure 5-7

Standby Supply

is defective

Protection

LED8004 is on?

Ye s

Go to operating voltages

don´t exist repair procedure for

V2 versions.

Switch on via Jig connector

switch.

Replace Power

supply board

Diagnostic software

Repair Scenario SDI PDP panels as stand alone V3 & V4 versions

Repair 42" & 50" SDV3

as Stand alone

Check PDP type number

PDP identification = S37SD-YD02 or YB01? S42SD-YD05 or YB03? S42AX-XD02 or XB01?

S50HW-XD03 or XB02?

3122 785 90770

Other PDP

type

EN 21S/SD/HD 3.1 PDP 5.

Disconnect and remove SSB FTP2.2

or LC4.7 board.

Remove plastic Frame to have acces to all boards

Connect Jig connector with switch to Sub Supply

CN9004 / CN9005

Set DIP switch 3 to internal mode

Position of DIP Switch Int or Ext is indicated on board

Connect set to Mains

CN8001 on Power Supply (use mains filter)

Green Stby LED

8003 is on ?

Ye s

Switch Jig connector switch on

Go to V2 repair scenario

1 2 3 4 1 2 3 4

Internal External

Standby Supply

is defective

Go to fault finding part

No Display Abnormal Display

Green LED 8001

& 8002 are on?

Ye s

Some horizontal or

Vertical Lines don´t exist

Figure 5-8

Protection

LED8004 is on?

Ye s

Go to operating voltages

don´t exist repair procedure for V3/V4

Versions.

Switch on via Jig connector switch.

Replace Power

supply board

EN 22 S/SD/HD 3.1 PDP5.

No Voltage output

Operating Voltages don´t exist

Diagnostic software

Fault Symptoms

First check complete set.

Fault Symptom?

Operating Voltages exist,

but No Display

Abnormal Display, not

open or short Lines

Some horizontal or Vertical

Lines don´t exist on the

Display.

Sustain open

Operating voltages don´t exist.

Go to

Version V2 or V3 / V4

Go to

No Display

Is related to Logic adress Buffer.

Go to Adress Open /

Adress Short

Go to

Abnormal Display

Vertical

Horizontal or

Vertical Lines?

Horizontal

Is related to X-Main, Y-Main and Y-

buffer.

Go to Sustain open /

Sustain short

Figure 5-9

Diagnostic software

No Display

EN 23S/SD/HD 3.1 PDP 5.

Operating voltages exist, but there

No Display is related with Y-Main,

Check Logic Main

Dip switch is on

Internal mode!

Check V-Sync

on test point logic

is no Display.

X-Main or Logic-main board

LED blinks?

Ye s

main board

No Display

Bring set in

repair set-up as standalone

Check Y-Main board

Wavefo rm on Y Buffer test point ?

Not OK

Check Fuse ?

Scavio or SSB is

disconnected and removed.

Power supply will be started-

up with Jig connector and

DIp swithc on Logic main is

on internal mode.

Check X-Main board

Wavefo rm

on X-board

test point ?

Not OK

Check Fuse ?

supply on Logic mains.

Logic main

normal state

Check Power

3V3 & 5V.

Not OK

Replace the Logic-

main board

Open

Ye s

Replace the

Y-main board

Not OK

Check FET

Short?

Check

Y Buffer Uper

and Lower?

Y-Main & Y-buffer

normal state

Replace Y buffer

Replace PDP Panel

Check FET

Short?

Open

Ye s

X-Main

normal State

Replace the

X-main board

Figure 5-10

EN 24 S/SD/HD 3.1 PDP5.

Logic-Main

Observation of

abnormal Display

Diagnostic software

Abnormal Display

Exept horizontal or Vertical Lines

Check FFC

Flat Foil Connections

between Logic-main, X-main and Y-

main

Y-Main Check

Check Fuses and FET

X-Main Check

Check Fuses and FET

Regular abnormal

pattern

Ye s

Replace the Logic-

main board

Logic main

normal state

Replace PDP

Not

correct

Check voltages.

Adjust Y waveform

Check Ramp

waveform on Y-board

(buffer)

Wavefo rm ?

Waveform is

Go to X-Main board

Check

Check X

Wavefo rm

waveform

Check voltages. Replace Y-Main

board

Check supply voltages or

replace X-Main board.

Not

correct

Waveform is

X main board seems to be OK.

Replace PDP

Figure 5-11

Wavefo rm ?

Waveform not

Replace X-Main

board

Diagnostic software

Some horizontal lines don´t exist on the Display.

Sustain open or short

Sustain Open

or Sustain Short

EN 25S/SD/HD 3.1 PDP 5.

Horizontal Lines

Some horizontal lines don´t

exist on Display

Y-FPC

Sustain open

Check connections

Y-buffer up & Low

Check FFC

Nok

Horizontal lines

Some horizontal lines appear

to be linked on Video

Y-FPC

Sustain Short

FPC damaged or connection

to PDP

Replace the panel (PDP) There is a defect on FPC

Change Y-Buffer

Upper or Lower

After changing buffer,

recheck the status

Not OK

Done

Defect is from buffer

Figure 5-12

EN 26 S/SD/HD 3.1 PDP5.

Diagnostic software

Some Vertical Lines don´t exists or are always on,

Adress Open or Adress Short.

A part of the Display is not addressed

Adress Open

Line Open Data Block Open 1/2 or 1/4 of Display is missing COF Block Open

Logic Main / FFC Check or change

interconnections

What is the status of

open?

Adress open is related with

Logic Main, Logic Buffer

, FFC, TCP and so on.

Logic Buffer

Check Va Supply

Check and / or

change E / F / G

Buffer

Line short Data Block short

Logic Main / FFC Check or change

interconnections

What is the status of

Short?

Adress Short

Adress short is related with

Logic Main, Logic Buffer,

FFC, TCP and so on.

Logic Buffer

Check Va supply

Check and / or

change E / F / G

Buffer

1 Line

or 1 Block

Ye s

Replace PDP

NOK

Half Block /

Half of Screen

Ye s

Replace Logic-Main/

Adress Buffer E or F or G/

FFC

1 Line

or 1 Block

Ye s

Replace PDP

Done

NOK

Half Block /

Half of Screen

Ye s

Replace Logic-Main/

Adress Buffer E or F or G/

FFC

Figure 5-13

Block Diagrams, Testpoint Overview, and Waveforms

6. Block Diagrams, Testpoint Overview, and Waveforms

6.1 Block Diagram for Logic circuit

42" SDv2

LOGIC CONTROL

LVDS

DATA_R

8Bits

DATA_G

8Bits

DATA_B

8Bits

DCLK

Vs ync

Hsync

Enable

In tupDataProcsesor

aD t

ao C

nt or ller

ARDM

T imi gnCt

rDver

i o n

oll e

Display

Data

Driver

Timing

Scan

Timing

rDive

oRw

et n

P u

are

s e

o r

DRIVER CIRCUIT & PANEL

852× 480 Pixels

852 × 3 × 48 0 Ce lls

Column Driver

Vdd

Vset Vsc

VsVa

Ve V3.3

eG n

era

ulse

to r

EN 27S/SD/HD 3.1 PDP 6.

42" SDv3

-V3.3 :

-V5 :

-Vdd :

-Va :

-Vs :

-Vsc :

-Ve :

-Vset :

Reference

Voltage for LOGIC Control Voltage for COF driver Voltage for FET driver Voltage for address pulse Voltage for sustain driver Voltage for scan pulse Voltage for X ramppulse Voltage for Y ramppulse

EN 28 S/SD/HD 3.1 PDP6.

42" HDv3

DATA_R

8Bits

DATA_G

8Bits

DATA_B

8Bits

DCLK

Vsync

Hsync

Enable

LVDS

Interface

LOGIC CONTROL

Input Data Processor

Data Controller

Block Diagrams, Testpoint Overview, and Waveforms

Display

DRAM

Data

Driver

Row

Timing Controller

Driver

Timing

Driver

Generator

YPulse

DRIVER CIRCUIT & PANEL

Column Driver

1024× 76 8 Pixe ls

1024× 3× 768 Cells

Sca n

Timing

Column Driver

Vcc

Vdd

Vset Vsc

VsVa

Generator

XPulse

S37" SDv4

DATA_R

8 Bits

DATA_G

8 Bits

DATA_B

8 Bits

DCLK

Vsync

Hsync

Enable

LVDS

Interface

LOGIC CONTROL

Input Data Processor

Data Controller

k

DRAM

k

Timing Controller

k

{

Driver

z 

{

Driver

Row

Generator

Y Pulse

Reference

- Vcc : Voltage for Logic Control

- Vdd : Voltage for Fet driver

- Va : Voltage for address pulse

- Vs : Voltage sustain pulse

- Vsc : Voltage for scan pulse

- Ve : Voltage for X ramp pulse

- Vset : Voltage for Y ramp pulse

DRIVER CIRCUIT & PANEL

Generator

852 x 480 Pixels

852 x 3 x 480 Cells

Column Driver

X Pulse

}

}

} }

}}

}

Reference

- Vcc : Voltage for Logic Control

- Vdd : Voltage for FET driver

- Va : Voltage for address pulse

- Vs : Voltage sustain pulse

- Vsc : Voltage for scan pulse

- Ve : Voltage for X ramp pulse

- Vset : Voltage for Y ramp pulse

50" HDv3

DATA_R

8(9 )Bi ts

DATA_G

8(9 )Bi ts

DATA_B

8(9 )Bi ts

DCLK

Vsync

Hsync

Enable

LVDS

Interface

Block Diagrams, Testpoint Overview, and Waveforms

LOGIC CONTROL

Display

Data

Driver

DRAM

Input Data Processor

Data Controller

Driver

Timing

Timing Controller

Sca n

Driver

Timing

Row

Generator

YPulse

Vset Vsc_l Vscan

DRIVER CIRCUIT & P ANEL

1366× 3× 768 Cells

Column Driver

1366× 768 Pixels

Column Driver

EN 29S/SD/HD 3.1 PDP 6.

Generator

XPulse

VsVaVcc Vdd

6.2 PSU Board diagram

42" SDv2

PFC

Reference

- Vcc : Voltage for Logic Control

- Vdd : Voltage for FET driver

- Va : Voltage for address pulse

- Vsc_l

: Voltage sustain low

- Vscan : Voltage for scan high

- Vb : Voltage for X bias

- Vset : Voltage for Y ramp pulse

COLDHOT

Vcc

8006

8005

8007

VSCAN

1 2

P10

P11

8003

8008

8010

P12

4 5

P13

P14

8004

COLD HOT

GREEN

8001

GREEN

8002

5V_STBY_S

HOT COLD

3V3_VSB_S

8V6 VFAN

Protection

GREEN

8003

8009

1510

P7 P6 P2 P1

DV5

RED

8002

P5 P3

8004

13413

Board

VSET

8001

CL 36532011_009.eps

8011

1812

5 1

050303

EN 30 S/SD/HD 3.1 PDP6.

42" SDv3

Block Diagrams, Testpoint Overview, and Waveforms

GND VSET

GND

VSCAN

GND VCC

D5VL

GND

9V_Standby

GND

8V6

GND

5V_SW

GND

12V

GND

POWER OK

5V_Relay Io_2

GND

DC Prot

PIPQ GND GND

GND

Temp Sensor

GND 5V2

T-VS

CN8003

T-VSCAN

T-VCC

CN8005

CN8006

T-VA

HIC8002

alarm B/D

T-VSET

CN8007CN8004

FAIL RED

LED8004

GND T-3V3

VCC

PFC

HOTCOLD

T-VCC-S

VR8004

HIC8003

VS sub B/D

VR8007

VR8006

D3V3

VR8003

VSET

VR8005

VSCAN

VR8009

D5VL

CN8008

T-5V 9V_Standby 5V2

VS_ON

5V2

GND

D3V3

D5VL

GND

CN8009

T-0V

T-VPFC

T-VE

HIC8001

PFC sub B/D

VR8002

VSB

VCC

D5VL

VR8008

T-PFC_VCC

GND

CN8002

GREEN

LED8001

GREEN

LED8002

GREEN

LED8003

GNDVSGND

DOWN

CN8001

AC INPUT

42" HDv3

GND VSET

GND

VSCAN

GND VCC

D5VL

GND

9V_Standby

GND

8V6

GND

5V_SW

GND

12V

GND

POWER OK

5V_Relay Io_2

GND

DC Prot

PIPQ

GND GND

GND

Temp Sensor

GND

5V2

T-VS

CN8003

T-VSCAN

T-VCC

CN8005

CN8006

T-VA

HIC8002

alarm B/D

T-VSET

CN8007CN8004

FAIL RED

LED8004

GND T-3 V3

VCC

PFC

HOTCOLD

T-VCC-S

VR8004

HIC8003

VS sub B/D

VR8007

VR8006

D3V3

VR8003

VSET

VR8005

VSCAN

VR8009

D5VL

CN8008

T-5V 9V_Standby 5V2

VS_ON

5V2

GND

D3V3

D5VL

GND

CN8009

T-0V

T-VPFC

T-VE

HIC8001

PFC sub B/D

VR8002

VSB

VCC

D5VL

VR8008

T-PFC_VCC

GND

CN8002

GREEN

LED8001

GREEN

LED8002

GREEN

LED8003

GND

CN8001

AC INPUT

DOWN

Block Diagrams, Testpoint Overview, and Waveforms

EN 31S/SD/HD 3.1 PDP 6.

S37" SDv4

D5VL

GND

Vscan

GND

Vset

GND GND

VS VS

D5VL

GND

CN8003

CN8005

No Output

voltage(V)

Voltage Setting

(Nominal Load λ)

1PFC

2 VS 160V ~ 185V

3 VA 65V ~ 80V

4 VE 150V ~ 170V

5 VSET 160V ~ 180V

6 VSCAN -55V ~ -75V

7 D5VL 4.0V ~ 6.0V

Check voltage label on the PDP

for correct values.

8 D3V3 2.8V ~ 4.0V

9 VCC Fixed

10 5V2 3.5V ~ 6.0V

11 9V_Standby Fixed

GND

D5VL

GND

CN8002

HOT(LIVE)

DC_VCC

VPFC

CN8008

VPFC

GND

BUFFER

VR8005

VR8009

VPFC

VR8001

Output Voltage

Variable Point

370V ~ 400V

8V_STBY

GND

+8.8 V

GND

+5.2V

GND +12V GND

POWER_OK

5V_Relay

GND

STANDBY

DC_PR07

PIRO

GND GND GND GND

THEM_SEN

+5V2

CN8004

IN-2

IN-3

VR8002

VSCAN

HIC8003

VSCAN

D5VL

VSET

+8.6V

+ 6.2V

+12V

D3V3

GND

AC_DET

POWER_OK

DC_PR07

PIRO

GND

PFC_OK

+6V2

CN8007

V9 VE

VA8003

A5SY CODE LJ44-00084A

VA8008

VSET

CN8006

D5VL

VS_ON

AC_DET

STANDBY

D3V3

GND

D5VL

RELAY

No Output

GND

D3V3

VR8004

SERIAL NO.

D3V3

voltage(V)

VR8006

D5VL

VA8007

D3V3

Ved j

L D8004

L D8003

Vuo

(Nominal Load λ)

VA8 20 8

+5V2

Voltage Setting

L D8001

HIC8002

HIC8001

PS-374-PH 20040420 ED05

2VS

3 VA 60V ~ 80V

4 VE 165V ~ 195V

5 VSET 160V ~ 180V

6 VSCAN -145V ~ -175V

7 D5VL 5.0V ~ 6.0V

8 D3V3 2.8V ~ 3.8V

Check voltage label on the PDP for

correct values.

9 VCC Fixed

10 5V2 4.5V ~ 5.6V

11 9V_Standby Fixed

PBA Flev

ABCDEFGH I 12345678 9

N AC INPUT L

100-240V ~ 50/60Hz 6.3 A

Output Voltage

Variable Point

160V ~ 185V

CN8001

EN 32 S/SD/HD 3.1 PDP6.

50" HDv3

V9 GND GND

Vset

GND

Yscan

GND

D6V

GND GND

VA VA

GND GND

VA VA

+9V_STBY

GND

8V8

GND

D5V_5W

GND

12V

GND

POWER_OK

+5V_RELAY_IDZ

GND

STAND_BY

DC_PROT_IN

PIRO

GND GND GND

THERMAL_DET

GND

+5V2

CN8002

CN8003

CN8006

V0 V6 D3V3 V0 D6V GND

+5V2

IV-2

CN8004

IV-3

CN8007

D5VL

BUFFER

GND

HJC8003

GND

VR8005

H8008

S/N

VR8009

COMP.SILK SCREEN

VR8004

D3V3

VR8007

+5VSB

VR8208

VR8006

D5V

Vedj

Vuo

Block Diagrams, Testpoint Overview, and Waveforms

DONGAH ELECOMM

P5-503-PHINZI

00M5510408191

1 OF 6

P5-503-PHINZ1 .PCB

DIPPING

A55V CODE : LJ44-00065A

COLD (ISOLATED)

H8005

PBA Rev HOT (LIVE)

COLD (ISOLATED)

CN8008

GND

D3V3

VS_ON

HOT (LIVE)

-P 1/6 -

H8004

ABCDEFGH 123456779

IV - 1

CN8009

GND

DC_VCC

PCB NAME VER. NO.

SHEET FILE NAME

UL6500:E240806.UL60950:E166582

H8003

VPFC

VR8001

VPFC

HC8001

CHECK

DESIGN

APPROVE

00MS5510408191

H8002

P5-503-PH

TOP

H8001

CAUTION

WARNING

CN8001

AC INPUT

100-240V ~ 50/60Hz BA

FOR CONTINUED PROTECTION AGAINST RISK OF FIRE,

REPLACE ONLY WITH SAME TYPE AND RATING OF FUSE.

No Output

voltage(V)

1PFC

Voltage Setting

(Nominal Load λ)

Output Voltage

Variable Point

370V ~ 400V

2 VS 160V ~ 185V

3 VA 65V ~ 80V

4 VE 150V ~ 170V

5 VSET 160V ~ 180V

6 VSCAN -55V ~ -75V

7 D5VL 4.0V ~ 6.0V

Check voltage label on the PDP

for correct values.

8 D3V3 2.8V ~ 4.0V

9 VCC Fixed

10 5V2 3.5V ~ 6.0V

11 9V_Standby Fixed

Circuit Diagrams and PWB Layouts

7. Circuit Diagrams and PWB Layouts

Not aplicable.

EN 33S/SD/HD 3.1 PDP 7.

EN 34 S/SD/HD 3.1 PDP8.

Aligments

8. Aligments

8.1 Adjustment Specification, Checking Position etc.

8.1.1 42" SDv2

1) Preparation

Insert Short Bar (J8002) in SMPS

  Connect Relay Jig S/W JIG 

Change Logic B’d S/W into internal mode

external Mode

1234 1234

 Insert Jig AC socket

Oscilloscope

 CH1: V-SYNC (CN201)  CH2: Y-output (OUT4)  CH3: X-output (TP OUT)  Connect Key-scan B’d

2) Turn-On.

- Turn on Power S/W

- Check LED in Logic B’d ()

- Check waveform of X-B’d nad Y-B’d (Refer to Picture 1)

Internal Mode

Vsync

Y-Output

X-Output

[Picture 1] Waveform of X-Board, Y-Board

How to adjust waveform

Aligments

EN 35S/SD/HD 3.1 PDP 8.

Procedure

1) Make Full White on Screen.

2) Observe waveform using Oscilloscope.

 check OUT4 TP in Y-buffer(upper). Observe the waveform of the third waveform of 1TV-Field.

 Adjust the division of oscilloscope like the left picture  Adjust the period of Vset as 10µS,

that of -Vsc(1) as 20µs, that of -Vsc(2) as 5µs, turning VR (Variable Resistor) (only,when you adjust each period of -Vsc(1) & -Vsc(2) adjust Vertical Division of oscilloscope as '2V or 5V')  VR for Vset : VR5003 (Y_main) VR for -Vsc(1) : VR5001 (Y_main) VR for -Vsc(2) : VR5002 (Y_main)

8.1.2 42" SDv3

V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)

rising maintance time

falling maintance time

Adjust VR5002 to set the time of

Yrr (Rising Ramp) 10 ㎲

Adjust VR5004 to set the voltage of

Vsch (Scan high voltage) 40 V

Adjust VR5003 to set the time of

Yfr (Falling Ramp_1st) 30 ㎲

Adjust VR5001 to set the time of

Yfr (Falling Ramp_3rd) 30 ㎲

EN 36 S/SD/HD 3.1 PDP8.

(t)

Aligments

Rising Ramp Falling Ramp

(V)

50V/div.

DC=0V

VR5004

20µs/div.

(V)

20V/div.

40V

50µs/div.

(t)

1. VR5004 Adjustment: Vsch TP => 40volt

2. VR5002 Adjustment: Rising Ramp flat time: Typ. 10 µsec

3. VR5003 Adjustment: Falling Ramp flat time => Typ. 30 µsec

4. VR5001 Adjustment: 3th SF Falling Ramp flat time => Typ. 30 µsec

* Pay close attention to above adjustment

* Dip Switch Mode

Internal

1 2 3 4

External

1 2 3 4

8.1.3 42" HDv3

(t)

V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)

rising maintance time

Aligments

falling maintance time

EN 37S/SD/HD 3.1 PDP 8.

(V)

50V/div.

DC=0V

Adjust VR5002 to set the time of

Yrr (Rising Ramp) 20 ㎲

Adjust VR5003 to set the time of

Yfr (Falling Ramp_1st) 20 ㎲

Rising Ramp Falling Ramp

20µs/div.

40V

Adjust VR5004 to set the voltage of

Vsch (Scan high voltage) 40 V

Adjust VR5001 to set the time of

Yfr (Falling Ramp_3rd) 10 ㎲

(V)

20V/div.

50µs/div.

(t)

EN 38 S/SD/HD 3.1 PDP8.

Aligments

VR5003

VR5004

VR5001

VR5005

VR5002VR5006

1. VR5004 / Adjustment; Clock-wise to max

2. VR5005/ Adiustment; Clock-wise to max

3. VR5001/ Adiustment; Clock-wise to 4

4. VR5002 Adjustment: Rising Ramp flat time:

=> Typ. 20usec

5. VR5006 Adjustment: Falling Ramp flat time

=> Typ. 20usec

6. VR5003 Adjustment: 3th SF Falling Ramp flat time

=> Typ. 10usec

division

* Pay close attention to above adjustment

* Dip Switch Mode

Internal

1 2 3 4

External

1 2 3 4

8.1.4 S37" SDv4

(t)

V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)

40 µs

16 µs

Adjust VR5001 to set the time of

Yrr( Rising Ramp) 40 µs

Aligments

Adjust VR5000 to set the time of

38 V

EN 39S/SD/HD 3.1 PDP 8.

Adjust VR5002 to set the time of Yfr

(Falling Ramp_1st) 16 µs

Rising Ramp Falling Ramp

(V)

50V/div.

DC=0V

20µs/div.

(V)

20V/div.

40V

50µs/div.

(t)

EN 40 S/SD/HD 3.1 PDP8.

Aligments

VR5003

VR5004

VR5001

VR5005

VR5002VR5006

1. VR5004 / Adjustment; Clock-wise to max

2. VR5005/ Adiustment; Clock-wise to max

3. VR5001/ Adiustment; Clock-wise to 4

4. VR5002 Adjustment: Rising Ramp flat time:

=> Typ. 20usec

5. VR5006 Adjustment: Falling Ramp flat time

=> Typ. 20usec

6. VR5003 Adjustment: 3th SF Falling Ramp flat time

=> Typ. 10usec

division

* Pay close attention to above adjustment

* Dip Switch Mode

Internal

1 2 3 4

External

1 2 3 4

8.1.5 50" HDv3

(t)

V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)

Aligments

EN 41S/SD/HD 3.1 PDP 8.

(V)

50V/div.

DC=0V

Adjust VR5000 to set the time of

Yrr( Rising Ramp) 50 µs

Adjust VR5001 to set the time of Yfr

(Falling Ramp_1st) 35 µs

Rising Ramp Falling Ramp

Adjust VR5901 to set the voltage of

Vsch [Scan high voltage ] 25V

Adjust VR5002 to set the time of

Yfr (Falling Ramp_3rd) 20 µs

(V)

20V/div.

40V

20µs/div.

50µs/div.

(t)

EN 42 S/SD/HD 3.1 PDP8.

Aligments

1. VR5901(Vscan_h) / Adjustment; 25V

2. VR5901/(Vscan) / Adjustment; -90V

3. VR5901/ Adiustment; Fix

4. VR5000 Adjustment: Rising Ramp flat time:

=> Typ. 50 µsec

5. VR5001 Adjustment : Falling Ramp flat time

=> Typ. 35 µsec

VR5001

VR5002

VR5006

* Pay close attention to above adjustment

* Dip Switch Mode

VR5000

6. VR5002 Adjustment : 3th SF Falling Ramp flat time

=> Typ. 20 µsec

VR5004 VR5005

External

Internal

1 2 3 4

Aligments

EN 43S/SD/HD 3.1 PDP 8.

8.2 Adjusting procedure

42" SDv3 (SDv2)

1. Get Pattern to be Full White.

2. Adjust Vsch to 40V with VR5004.

3. Check the waveform with an Oscilloscope.

• Triggering through V-sync of LOGIC Board.

• Connect the OUT 4 Test Point at the center of Y_buffer to other channel, and then check the first SF operating waveform of 1TV-Field.

• Check the waveform as before by adjusting Horizontal Division. Check the Reset waveform when the V_TOGG Level is changed.

• Set the Vset to 10µsby adjusting VR5002.

• Set the Falling maintenance time to 30µs by adjusting R5003.

• Change the waveform position of Oscilloscope to 3SF and then set the Falling maintenance time to 30µsby adjusting the VR5001. GND maintenance section should be checked after the Vertical Division is readjusted to '2V or 5V'.

Special Notice: When you adjust the inclination of waveform, do check and adjustment being based on the Reset waveform of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for adjusting.

42" HDv3

1. Get Pattern to be Full White.

2. Adjust Vsch to Clock-wise max by using VR5004 (Vsch should be connected to "+" unit of DMM).

3. Check the waveform using Oscilloscope.

• Triggering through V_TOGG of LOGIC Board.

• Connect the OUT 4 Test Point at the center of Y_buffer

to other channel, and then check the first SF operating waveform of 1TV-Field.

• Check the waveform as before by adjusting Horizontal

Division. Check the Reset waveform when the V_TOGG Level is changed.

• Set the Vset to 20µs by adjusting VR5002. GND

maintenance section should be checked after the Vertical Division is readjusted to '2V or 5V'.

• Set the Falling maintenance time to 20µs by adjusting

R5006.

• Change the waveform position of Oscilloscope to 3SF

and then set the Falling maintenance time to 10µs by adjusting the VR5003. GND maintenance section should be checked after the Vertical Division is readjusted to '2V or 5V'.

Special Notice: When you adjust the inclination of waveform, do check and adjustment being based on the Reset waveform of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for adjusting.

S37" SDv4

1. Get Pattern to be Full White.

2. Adjust Vsch to 40V by using VR5004 (Vsch should be connected to "+" unit of DMM). Vsch is over 95V than Vsc_l.

3. Check the waveform using Oscilloscope.

• Triggering through V_TOGG of LOGIC Board.

• Connect the OUT 4 Test Point at the center of Y_buffer

to other channel, and then check the first SF operating waveform of 1TV-Field.

• Check the waveform as before by adjusting Horizontal

Division. Check the Reset waveform when the V_TOGG Level is changed.

• Set the Vset to 40µs by adjusting VR5001. GND

maintenance section should be checked after the Vertical Division is readjusted to '2V or 5V'.

• Set the Falling maintenance time to 16µs by adjusting

R5002.

• Change the waveform voltage GND to 38V by adjusting the VR5000.

Special Notice: When you adjust the inclination of waveform, do check and adjustment being based on the Reset waveform of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for adjusting.

50" HDv3

1. Get Pattern to be Full White.

2. Adjust Vsch to 25V by using VR5901_VSC_h (Vsc_h should be connected to "+" unit of DMM).

3. Check the waveform using Oscilloscope.

• Triggering through V_TOGG of LOGIC Board.

• Connect the OUT 4 Test Point at the center of Y_buffer

to other channel, and then check the first SF operating waveform of 1TV-Field.

• Check the waveform as before by adjusting Horizontal

Division. Check the Reset waveform when the V_TOGG Level is changed.

• Set the Rising Ramp Flat Time to 50µs by adjusting

VR5000. GND maintenance section should be checked after the Vertical Division is readjusted to '2V or 5V'.

• Set the Falling maintenance time to 35µs by adjusting

R5001.

• Change the waveform position of Oscilloscope to 3SF

and then set the Falling maintenance time to 20µs by adjusting the VR5002.

• GND maintenance section should be checked after the

Vertical Division is readjusted to '2V or 5V'.

Special Notice: When you adjust the inclination of waveform, do check and adjustment being based on the Reset waveform of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for adjusting.

Alignment table Y PWB

Wave Form Adjusting

37SDV4 Rising_Ramp VR5001 30 µs (30 ~ 40)

Falling_Ramp_1st VR5002 16 µs (10 ~ 20)

Vsch VR5000 38V

42SDV2 Rising_Ramp (Vset) VR5003 10 µs

-Vsc 1 VR5001 20 µs

-Vsc 2 VR5002 5 µs

42SDV3 Rising_Ramp VR5002 10 µs

Falling_Ramp_1st VR5003 30 µs

Falling_Ramp_3rd VR5001 30 µs

Vsch VR5004 40V

42HDV3 Rising_Ramp VR5002 10 µs

Falling_Ramp_1st VR5003 20 µs

Falling_Ramp_3rd VR5001 10 µs

Vsch Scan high voltage

50HDV3 Rising_Ramp VR5000 50 µs

Falling_Ramp_1st VR5001 35 µs

Falling_Ramp_3rd VR5002 20 µs

Vsch Scan high voltage

Location No

VR5004 40V

VR5901 25V

Default

EN 44 S/SD/HD 3.1 PDP9.

9. Circuit Descriptions

Circuit Descriptions

9.1 Main function of Each Assembly

9.1.1 X-main board

The X-main board generate a drive signal by switching the FET in synchronization with logic main board timing and supplies the X electrode of the panel with the drive signal through the connector.

1. Maintain voltage waveforms (including ERC)

2. Generate X rising ramp signal

3. Maintain Ve bias between Scan intervals

9.1.2 Y-main board

The Y-main board generate a drive signal by switching the FET in synchronization with the logic Main Board timing and sequentially supplies the Y electrode of the panel with the drive signal through the scan driver IC on the Y-buffer board. This board connected to the panel’s Y terminal has the following main functions.

1. Maintain voltage waveforms (including ERC)

2. Generate Y-rising Falling Ramp

3. Maintain V scan bias

9.2 Abbrevitation

TCP Tape Carrier Package

FFC Flat Foil Cable (connection)

COF Circuit on Foil

FPC Flexible Printed Circuit

Vsc H or Vsc L V Scan High or Low

SF Sub Frame

Vset RR Vset Raising Ramp (Flat time)

Vset FR Vset Falling Ramp (flat time)

VR Variable resistor

YBU & YBL

YBM

9.1.3 Logic main board

The logic main board generates and outputs the address drive output signal and the X ,Y drive signal by processing the video signals. This Board buffers the address dirve output signal and feeds it to the address drive IC (COF module, video signal- X Y drive signal generation , frame memory circuit / address data rearrangement).

9.1.4 Logic buffer(E,F)

The logic buffer transmits data signal and control signal.

9.1.5 Y-buffer board (Upper, Lower)

The Y-buffer board consisting of the upper and lower boards supplies the Y-terminal with scan waveforms. The board comprises 8 scan driver IC’s (ST microelectronics STV 7617 : 64 or 65 output pins) , but 4 ICs for the SD class.

9.1.6 AC Noise Filter

The AC Noise filter has function for removing noise(low Frequency) and blocking surge. It effects Safety standards (EMC,EMI).

9.1.7 TCP( Tape Carrier Package )

The TCP applies Va pulse to the address electrode and constitutes address discharge by the potential difference between the Va pulse and the pulse applied to the Y electrode. The TCP comprise 4 data driver Ics(STV7610A :96 pins output pins) 7 TCPs are required for signal scan.

10. Spare Parts List

Spare Parts List

EN 45S/SD/HD 3.1 PDP 10.

42"SDv2

PDP type

S42SD-YD06 9322 195 45682 PDP model name

S42SD-YB04 9965 000 17797 PDP without PSU

(non spare)

BOARDS

LJ92-00632A 9965 000 17726 Logic-Buffer(E) LJ92-00633A 9965 000 17725 Logic-Buffer(F) LJ92-00634A 9965 000 17724 Logic-Buffer(G) LJ92-00751A 9965 000 17727 Y-Buffer(up) LJ92-00750A 9965 000 17728 Y-Buffer(down) LJ92-00818A 9965 000 17729 Logic-Board LJ92-00998A 9965 000 17720 X-Board LJ92-00999A 9965 000 17731 Y-Board LJ44-00049A 9965 000 17730 SMPS(PSU)

42"SDv3

PDP type

S42SD-YD05 9322 215 27682 PDP model name

S42SD-YB03 9965 000 25997 PDP without PSU

BOARDS

LJ92-00811A 9965 000 25109 Logic-Buffer(E) LJ92-00812A 9965 000 25110 Logic-Buffer(F) LJ92-00813A 9965 000 25111 Logic-Buffer(G) LJ92-00796A 9965 000 25112 Y-Buffer(up) LJ92-00797A 9965 000 25113 Y-Buffer(down) LJ92-00975D 9965 000 25114 Logic-Board LJ92-00943A 9965 000 25115 X-Board LJ92-00944B 9965 000 25116 Y-Board LJ44-00058A 9965 000 25108 SMPS(PSU) LJ44-00075A 9965 000 25131 SUB PSU

(non spare)

50"HDv3

PDP type

S50HW-XD03 9322 215 26682 PDP model name

S50HW-XB02 9966 000 26017 PDP without PSU

BOARDS

LJ92-00917A 9965 000 25117 Logic-Buffer(E) LJ92-00918A 9965 000 25118 Logic-Buffer(F) LJ92-00919A 9965 000 25119 Logic-Buffer(G) LJ92-00920A 9965 000 25120 Logic-Buffer(H) LJ92-00921A 9965 000 25121 Logic-Buffer(I) LJ92-00922A 9965 000 25122 Logic-Buffer(J) LJ92-00880A 9965 000 25123 Y-Buffer(up) LJ92-00881A 9965 000 25124 Y-Buffer(down) LJ92-00949C 9965 000 25125 Logic-Board LJ92-00923A 9965 000 25126 SUBL LJ92-00959A 9965 000 25127 SUBR LJ92-00852A 9965 000 25128 X-Board LJ92-00853A 9965 000 25129 Y-Board LJ44-00065A 9965 000 25130 SMPS(PSU) LJ44-00099A 9965 000 26195 SUB PSU

(non spare)

37"SDv4

PDP type

S37SD-YD02 8204 000 77261 PDP model name

S37SD-YB01 9965 000 26018 PDP without PSU

(non spare)

BOARDS

LJ92-00976A 9965 000 26187 Logic-Buffer(E) LJ92-00977A 9965 000 26188 Logic-Buffer(F) LJ92-01002A 9965 000 26189 Logic-Buffer(G) LG92-01022A 9965 000 26190 Y-Buffer(up) LJ92-01056A 9965 000 26191 Logic-Board LJ92-01020A 9965 000 26192 X-Board LJ92-01021A 9965 000 26193 Y-Board LJ44-00084A 9965 000 26194 SMPS(PSU) LJ44-00075A 9965 000 25131 SUB PSU

42"HDv3 *not used in Eu sets

PDP type

S42AX-XD02 9322 215 25682 PDP model name

S42AX-XB01 9965 000 26016 PDP without PSU

BOARDS

LJ92-00895A 9965 000 25101 Logic-Buffer(E) LJ92-00896A 9965 000 25102 Logic-Buffer(F) LJ92-00994A 9965 000 25103 Y-Buffer(up) LJ92-00993A 9965 000 25104 Y-Buffer(down) LJ92-00990E 9965 000 25105 Logic-Board LJ92-00980A 9965 000 25106 X-Board LJ92-00981A 9965 000 25107 Y-Board LJ44-00058A 9965 000 25108 SMPS(PSU) LJ44-00075A 9965 000 25131 SUB PSU

(non spare)

EN 46 S/SD/HD 3.1 PDP10.

Spare Parts List

Philips LC4.7, FM242(FTV2.1), FTP1.1, FTP2.2 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual

Technical Specifications

1. Technical Specifications

1.1 Model / Chassis overview

PDP Type Model Name H x V Pixel Chassis

37”SDv4 S37SD-YD02 (*)

42”SDv2 S42SD-YD06 (*)

42”SDv3 S42SD-YD05 (*)

42”HDv3 S42AX-XD03 (*)

50HDv3 S50HW-XD03 (*)

(*) are Model names with PSU, but only PDP model without PSU will be delivered as spare part

852 x 480 LC4.7

852 x 480 FM242

852 x 480 LC4.7

1024 x 768 FTP2.2U

1366 x 768 FTP2.2E

42" SDv2

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

42" SDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Figure 1-2

Points of Screw Mount

Figure 1-1

Figure 1-3

42"HDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Figure 1-4

Points of Screw Mount

Points of Screw Mount

Figure 1-7

50" HDv3

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU

Figure 1-5

37" SDv4

External View

M3 = X Board + Y Board + Logic Board + PSU + SUB PSU ‘

Figure 1-8

Points of Screw Mount

Figure 1-9

Figure 1-6

1.2 Serial Number

Figure 1-10

1.3 Specifications

No Item Specification 37” SDV4 Specification 42” SDV2 (ypo6)

1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells) 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)

2 Number of Cells 2556 (H) x 480 (V) 2556 (H) x 480 (V)

3 Pixel Pitch 0.960 (H) mm x 0.960 (V) mm 1.095 (H) mm x 1.110 (V) mm

4 Cell Pitch R 0.320 (H) mm x 0.960 (V) mm R 0.324 (H) mm x 1.110 (V) mm

G 0.320 (H) mm x 0.960 (V) mm G 0.365 (H) mm x 1.110 (V) mm

B 0.320 (H) mm x 0.960 (V) mm B 0.406 (H) mm x 1.110 (V) mm

5 Display size

6 Screen size Diagonal 37" Color Plasma Display Module Diagonal 42" Color Plasma Display Module

7 Screen aspect 16 : 9 16 : 9

8 Display color 16.77 million colors 16.77 million colors

9 Viewing angle

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm 982 (W) x 582 (H) x 52.9 (D) mm

11 Weight Module 1 About 15.5 kg Module 1 About 16.6 kg

PL42SD003C 60Hz/ 50Hz, LVDS PL42SD003C 60Hz/ 50Hz, LVDS

932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98 inch ]

No Item Specification 42” SDV3

1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)

2 Number of Cells 2556 (H) x 480 (V)

3 Pixel Pitch 1.095 (H) mm x 1.110 (V) mm

4 Cell Pitch R 0.365 (H) mm x 1.110 (V) mm

G 0.365 (H) mm x 1.110 (V) mm

B 0.365 (H) mm x 1.110 (V) mm

5 Display size

932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98 inch ]

6 Screen size Diagonal 42" Color Plasma Display Module

7 Screen aspect 16 : 9

8 Display color 16.77 million colors

9 Viewing angle

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm