Philips L6910 Service Manual

L6910

L6910A

ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION

FEATURE

■OPERATING SUPPLY VOLTAGE FROM 5V TO 12V BUSES

■UP TO 1.3A GATE CURRENT CAPABILITY

■ADJUSTABLE OUTPUT VOLTAGE

■N-INVERTING E/A INPUT AVAILABLE

■0.9V ±1.5% VOLTAGE REFERENCE

■VOLTAGE MODE PWM CONTROL

■VERY FAST LOAD TRANSIENT RESPONSE

■0% TO 100% DUTY CYCLE

■POWER GOOD OUTPUT

■OVERVOLTAGE PROTECTION

■HICCUP OVERCURRENT PROTECTION

■200kHz INTERNAL OSCILLATOR

■OSCILLATOR EXTERNALLY ADJUSTABLE FROM 50kHz TO 1MHz

■SOFT START AND INHIBIT

■PACKAGES: SO-16 & HTSSOP16

APPLICATIONS

■SUPPLY FOR MEMORIES AND TERMINATIONS

■COMPUTER ADD-ON CARDS

■LOW VOLTAGE DISTRIBUTED DC-DC

■MAG-AMP REPLACEMENT

BLOCK DIAGRAM

SO-16 (Narrow)	HTSSOP16 (Exposed Pad)
ORDERING NUMBERS:
L6910 (SO-16)	L6910A (HTSSOP16)

L6910TR (Tape & Reel) L6910ATR (Tape & Reel)

DESCRIPTION

The device is a pwm controller for high performance dc-dc conversion from 3.3V, 5V and 12V buses.

The output voltage is adjustable down to 0.9V; higher voltages can be obtained with an external voltage divider.

High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A.

The device assures protections against load overcurrent and overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode.

				Vin 5V to12V
		PGOOD	VCC	OCSET
				BOOT
	VREF
	SS	Monitor		UGATE
		Protection and Ref
	OSC	OSC		PHASE
		L6910		Vo
	RT			LGATE
			-	PGND
	EAREF	E/A	+	PWM
		+
		-		GND
		300k
				VFB
		COMP

October 2003

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L6910A L6910

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit
Vcc	Vcc to GND, PGND	15	V
VBOOT-	Boot Voltage	15	V
VPHASE
VHGATE-		15	V
VPHASE
	OCSET, LGATE, PHASE	-0.3 to Vcc+0.3	V
	SS, FB, PGOOD, VREF, EAREF, RT	7	V
	COMP	6.5	V
Tj	Junction Temperature Range	-40 to 150	°C
Tstg	Storage temperature range	-40 to 150	°C
Ptot	Maximum power dissipation at Tamb = 25°C	1	W

THERMAL DATA

Symbol	Parameter	SO-16	HTSSOP16	HTSSOP16 (*)	Unit
Rth j-amb	Thermal Resistance Junction to Ambient	120	110	50	°C/W

(*) Device soldered on 1 S2P PC board

PINS CONNECTION (Top view)

VREF	1	16	N.C.	VREF	1	16	VCC
OSC	2	15	VCC	OSC	2	15	LGATE
OCSET	3	14	LGATE	OCSET	3	14	PGND
SS/INH	4	13	PGND	SS/INH	4	13	BOOT
COMP	5	12	BOOT	N.C.	5	12	HGATE
FB	6	11	HGATE	COMP	6	11	PHASE
GND	7	10	PHASE	FB	7	10	PGOOD
EAREF	8	9	PGOOD	GND	8	9	EAREF
		SO16				HTSSOP-16

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			L6910A L6910
PINS FUNCTION
SO	HTSSOP	Name	Description
1	1	VREF	Internal 0.9V ±1.5% reference is available for external regulators or for the internal error
			amplifier (connecting this pin to EAREF) if external reference is not available.
			A minimum 1nF capacitor is required.
			If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.
2	2	OSC	Oscillator switching frequency pin. Connecting an external resistor (RT) from this pin to
			GND, the external frequency is increased according to the equation:
			4.94 × 106
			fO SC,RT = 200KHz + ------------------------
			RT (KW)
			Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced
			according to the equation:
			4.306 × 107
			fO SC,RT = 200KHz – ----------------------------
			RT(KW)
			If the pin is not connected, the switching frequency is 200KHz.
			The voltage at this pin is fixed at 1.23V. Forcing a 50mA current into this pin, the built in
			oscillator stops to switch.
			In Over Voltage condition this pin goes over 3V until that conditon is removed.
3	3	OCSET	A resistor connected from this pin and the upper Mos Drain sets the current limit
			protection.
			The internal 200mA current generator sinks a constant current through the external
			resistor. The Over-Current threshold is due to the following equation:
			IOCSE T × RO CS ET
			IP = ---------------------------------------------
			RDS on
4	4	SS/INH	The soft start time is programmed connecting an external capacitor from this pin and
			GND. The internal current generator forces through the capacitor 10mA.
			This pin can be used to disable the device forcing a voltage lower than 0.4V
5	6	COMP	This pin is connected to the error amplifier output and is used to compensate the voltage
			control feedback loop.
6	7	FB	This pin is connected to the error amplifier inverting input and is used to compensate the
			voltage control feedback loop.
			Connected to the output resistor divider, if used, or directly to Vout, it manages also over-
			voltage conditions and the PGOOD signal
7	8	GND	All the internal references are referred to this pin. Connect it to the PCB signal ground.
8	9	EAREF	Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to
			3V) for the PWM regulation or short it to VREF pin to use the internal reference.
			If this pin goes under 650mV (typ), the device shuts down.
9	10	PGOOD	This pin is an open collector output and it is pulled low if the output voltage is not within the
			above specified thresholds. If not used it may be left floating.
10	11	PHASE	This pin is connected to the source of the upper mosfet and provides the return path for the
			high side driver. This pin monitors the drop across the upper mosfet for the current limit
			together with OCSET.
11	12	HGATE	High side gate driver output.
12	13	BOOT	Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
			mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc
			(cathode vs. boot).
13	14	PGND	Power ground pin. This pin has to be connected closely to the low side mosfet source in
			order to reduce the noise injection into the device
14	‘5	LGATE	This pin is the lower mosfet gate driver output
15	16	VCC	Device supply voltage. The operative supply voltage ranges is from 5V to 12V.
			DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC.
16	5	N.C.	This pin is not internally bonded. It may be left floating or connected to GND.
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L6910A L6910

ELECTRICAL CHARACTERISTICS (Vcc = 12V, TJ =25°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min	Typ	Max	Unit
Vcc SUPPLY CURRENT
Icc	Vcc Supply current	OSC = open; SS to GND	4	7	9	mA
POWER-ON
	Turn-On Vcc threshold	VOCSET = 4V	4.0	4.3	4.6	V
	Turn-Off Vcc threshold	VOCSET = 4V	3.8	4.1	4.4	V
	Rising VOCSET threshold			1.24	1.4	V
	Turn On EAREF threshold	VOCSET = 4V		650	750	mV
SOFT START AND INHIBIT
Iss	Soft start Current	SS = 2V	6	10	14	μA
	S.S. current in INH condition	SS = 0 to 0.4V		35	60	μA
OSCILLATOR
fOSC	Initial Accuracy	OSC = OPEN	180	200	220	KHz
		OSC = OPEN; Tj = 0° to 125°	170		230	kHz
fOSC,RT	Total Accuracy	16 KΩ < RT to GND < 200 KΩ	-15		15	%
Vosc	Ramp amplitude			1.9		V
REFERENCE
VOUT	Output Voltage Accuracy	VOUT = VFB; VEAREF = VREF	0.886	0.900	0.913	V
VREF	Reference Voltage	CREF = 1nF; IREF = 0 to 100μA	0.886	0.900	0.913	V
VREF	Reference Voltage	CREF = 1nF; TJ = 0 to 125°C	-2		+2	%
ERROR AMPLIFIER
IEAREF	N.I. bias current	VEAREF = 3V		10		μA
	EAREF Input Resistance	Vs. GND		300		kΩ
IFB	I.I. bias current	VFB = 0V to 3V		0.01	0.5	μA
VCM	Common Mode Voltage		0.8		3	V
VCOMP	Output Voltage		0.5		4	V
GV	Open Loop Voltage Gain		70	85		dB
GBWP	Gain-Bandwidth Product			10		MHz
SR	Slew-Rate	COMP = 10pF		10		V/μs
GATE DRIVERS
IHGATE	High Side	VBOOT - VPHASE = 12V	1	1.3		A
	Source Current	VHGATE - VPHASE = 6V
RHGATE	High Side	VBOOT - VPHASE = 12V		2	4	Ω
	Sink Resistance
ILGATE	Low Side Source Current	Vcc = 12V; VLGATE = 6V	0.9	1.1		A
RLGATE	Low Side Sink Resistance	Vcc = 12V		1.5	3	Ω
	Output Driver Dead Time	PHASE connected to GND	90		210	ns
PROTECTIONS
IOCSET	OCSET Current Source	VOCSET = 4V	170	200	230	μA
	Over Voltage Trip (VFB / VEAREF)	VFB Rising		117	120	%
IOSC	OSC Sourcing Current	VFB > OVP Trip	15	30		mA
POWER GOOD
	Upper Threshold (VFB / VEAREF)	VFB Rising	108	110	112	%
	Lower Threshold (VFB / VEAREF)	VFB Falling	88	90	92	%
	Hysteresis (VFB / VEAREF)	Upper and Lower threshold		2		%
VPGOOD	PGOOD Voltage Low	IPGOOD = -4mA		0.4		V
IPGOOD	Output Leakage Current	VPGOOD = 6V		0.2	1	μA
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L6910A L6910

Device Description

The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is used (simply connecting together EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/ms slew rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The de-

vice monitors the current by using the rDS(ON) of the upper MOSFET(s) that eliminates the need for a current sensing resistor. The device is available in SO16 narrow package.

Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50mA (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between OSC pin and GND or VCC. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin.

In particular connecting RT vs. GND the frequency is increased (current is sunk from the pin), according to the following relationship:

4.94 × 106 fOSC,RT = 200KHz + -------------------------

RT (KW)

Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships:

	fOSC,RT =	200KHz –	4.306 × 10			7	VCC = 12V
			----	R-----T---(---K----W-----)---		-
	fOSC,RT	= 200KHz	–	15	× 106		VCC = 5V
				R-----T---	(---K----W-----)-

Switching frequency variation vs. RT are repeated in Fig. 1.

Note that forcing a 50mA current into this pin, the device stops switching because no current is delivered to the oscillator.

Figure 1.

	10000
	1000
[kOhm]
Resistance	100
		RT to GND
	10
		RT to VCC=12V
		RT to VCC=5V
	10	100	1000

Frequency [kHz]

Reference

A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid instability in the internal linear regulator. It is able to deliver up to 100mA and may be used as reference for the device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed.

Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-in- verting input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this pin can range from 0.9V to 3V. It has an internal pull-down (300kW resistor) that forces the device shutdown if no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is lower than 650mV (typ).

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L6910A L6910

Soft Start

At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is of 35μA and speeds-up the charge of the capacitor up to 0.5V. After that it becames 10μA until the final charge value of approximatively 4V.

When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase.

No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.

If VCC and OCSET pins are not above their own turn-on thresholds and VEAREF is not above 650mV, the SoftStart will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-

voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.

Figure 2. Soft Start (with Reference Present)

Vcc	Vcc Turn-on threshold
Vin
	Vin Turn-on threshold
Vss	1V
	to GND
	0.5V
LGATE
Vout

	Timing Diagram	Acquisition: CH1 = PHASE; CH2 = Vout;
		CH3 = PGOOD; CH4 = Vss

Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition.

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.

Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the high side turn-off.

The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V.

Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.

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L6910A L6910

Figure 3. High Side driver peak current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)

CH1 = High Side Gate CH4 = Gate Current

Figure 4. Low Side driver peak current. VCC = 12V (right) VCC = 5V (left)

CH1 = Low Side Gate CH4 = Gate Current

Monitoring and Protections

The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the powergood output is forced low.

The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.) greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the over-voltage is detected.

Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the

RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship:

I ROCS × IOCS

P = --------------------------------

RdsON

Where the typical value of IOCS is 200mA. To calculate the ROCS value it must be considered the maximum RdsON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied:

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L6910A L6910

I		³ I		DI		I
	P		OUT MAX	+ ----	=		PE AK
				2

Where DI is the inductance ripple current and IOUTMAX is the maximum output current.

In case of over current detectionthe soft start capacitor is discharged with constant current (10mA typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode, as shown in figure 5. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on.

Figure 5. Hiccup Mode

Figure 6. Inductor ripple current vs. Vout

	9		L=1.5μH, Vin=12V
	8
[A]	7			L=2μH,
				Vin=12V
Ripple	6
	5			L=3μH,
				Vin=12V
	4			L=1.5μH,
Inductor
	3			Vin=5V
				L=2μH,
	2
				Vin=5V
	1		L=3μH, Vin=5V
	0
	0 .5	1.5	2.5	3 .5

CH1 = SS; CH4 = Inductor current

Output V oltage [V]

Inductor design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current DIL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship:

VIN – VOUT	×	VOUT
L = -----f--sw--------×---D----I--L------		--------------
		VIN

Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 6 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V.

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required.

The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for DI load transient in case of enough fast compensation network response:

tapplication =	---------L-----×---D----I---------	tremoval	= --L----×---D----I-
	VIN – VOUT		VOUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.

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