Philips hef4724b DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4724B
MSI
8-bit addressable latch
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
8-bit addressable latch
DESCRIPTION
The HEF4724B is an 8-bit addressable latch with three
address inputs (A0to A2), a data input (D), an active LOW
enable input (E), an active HIGH clear input (CL), and eight
parallel latch outputs (O0to O7).
WhenE and CL are HIGH, all outputs (O0to O7) are LOW.
Eight-channel demultiplexing or active HIGH 1-of-8
decoding with output enable operation occurs when CL is
HIGH and E is LOW. When CL and E are LOW, the
HEF4724B
MSI
selected output (O
D. When E goes HIGH, the contents of the latch are
stored. When operating in the addressable latch mode
(E = CL = LOW), changing more than one bit of A0to
A2could impose a transient wrong address. Therefore,
this should only be done while in the memory mode
(E = HIGH, CL = LOW).
to O7; determined by A0to A2) follows
0
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4724BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4724BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4724BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
A
to A
0
2
A data input
E enable input (active LOW)
CL clear input (active HIGH)
to O
O
0
7
FAMILY DATA, IDDLIMITS category MSI
address inputs
parallel latch outputs
January 1995 2
See Family Specifications
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January 1995 3
Philips Semiconductors Product specification
8-bit addressable latch
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
HEF4724B
MSI
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