Philips HEF4526BT, HEF4526BPB, HEF4526BP, HEF4526BDB, HEF4526BD Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4526B MSI

Programmable 4-bit binary down counter

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Programmable 4-bit binary down counter

HEF4526B

MSI

DESCRIPTION

The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a terminal count output (TC) and an overriding asynchronous master reset input (MR).

This device is a programmable, cascadable down counter with a decoded TC output for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required.

Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW to HIGH transition of CP0.

When PL is LOW and CP0 is HIGH, the counter advances

on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (O0 = O1 = O2 = O3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of other input conditions.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Fig.1 Functional diagram.

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

Philips Semiconductors	Product specification

Programmable 4-bit binary down counter

HEF4526B

MSI

HEF4526BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4526BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4526BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

			Fig.2 Pinning diagram.
PINNING
	PL		parallel load input
	P0 to P3		parallel inputs
	CF		cascade feedback input
	CP0		clock input (LOW to HIGH, triggered)
			clock input (HIGH to LOW, triggered)
	CP	1
	MR		asynchronous master reset input
	TC		terminal count output
	O0 to O3		buffered parallel outputs

COUNTING MODE

CF = HIGH; PL = LOW; MR = LOW

	COUNT		OUTPUTS
		O3	O2	O1	O0
	15	H	H	H	H
	14	H	H	H	L
	13	H	H	L	H
	12	H	H	L	L
	11	H	L	H	H
	10	H	L	H	L
	9	H	L	L	H
	8	H	L	L	L
	7	L	H	H	H
	6	L	H	H	L
	5	L	H	L	H
	4	L	H	L	L
	3	L	L	H	H
	2	L	L	H	L
	1	L	L	L	H
	0	L	L	L	L

FUNCTION TABLE

MR	PL	CP0
			CP1			MODE
H	X	X		X		reset (asynchronous)
L	H	X		X		preset (asynchronous)
L	L			H		no change
L	L	L				no change
L	L			X		no change
L	L	X				no change
L	L			L		counter advances
L	L	H				counter advances

Notes

1.H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial

= positive-going transition

= negative-going transition

January 1995

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