Philips hef4526b DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4526B
MSI
Programmable 4-bit binary down
counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
DESCRIPTION
The HEF4526B is a synchronous programmable 4-bit
binary down counter with an active HIGH and an active
LOW clock input (CP0, CP1), an asynchronous parallel
load input (PL), four parallel inputs (P0to P3), a cascade
feedback input (CF), four buffered parallel outputs (O0to
O3), a terminal count output (TC) and an overriding
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
Information on P
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL andCP1are LOW, the
counter advances on a LOW to HIGH transition of CP0.
When PL is LOW and CP0 is HIGH, the counter advances
on a HIGH to LOW transition of CP1. TC is HIGH when the
counter is in the zero state (O0=O1=O2=O3= LOW)
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O0to O3= LOW) independent of other input
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
HEF4526B
MSI
to P3 is loaded into the counter while PL
0
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Philips Semiconductors Product specification
Programmable 4-bit binary down counter
Fig.2 Pinning diagram.
PINNING
PL parallel load input
P
to P
0
3
CF cascade feedback input
CP
0
CP
1
MR asynchronous master reset input
TC terminal count output
O
to O
0
parallel inputs
clock input (LOW to HIGH, triggered)
clock input (HIGH to LOW, triggered)
buffered parallel outputs
3
HEF4526B
MSI
HEF4526BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4526BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4526BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
COUNTING MODE
CF = HIGH; PL = LOW; MR = LOW
OUTPUTS
COUNT
O
3
O
2
O
1
15 H H H H
14 H H H L
13 H H L H
12 H H L L
11 H L H H
10 H L H L
9HLLH
8HLLL
7LHHH
6LHHL
5LHLH
4LHLL
3LLHH
2LLHL
1LLLH
0LLLL
FUNCTION TABLE
MR PL CP
O
0
H X X X reset (asynchronous)
CP
0
1
MODE
L H X X preset (asynchronous)
L L H no change
L L L no change
L L X no change
L L X no change
L L L counter advances
L L H counter advances
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
January 1995 3
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