Philips HEF4521BU, HEF4521BT, HEF4521BPB, HEF4521BP, HEF4521BDB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4521B MSI
24-stage frequency divider and oscillator
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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24-stage frequency divider and oscillator
HEF4521B
MSI
DESCRIPTION
The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (I2/O2) will function as a crystal oscillator, or in combination with I1 as an RC oscillator, or as an input buffer for an external oscillator. Low-power
operation as a crystal oscillator is enabled by connecting external resistors to pins 3 (VSS’) and 5 (VDD’).
Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B will count up to
224 = 16777216. The counting advances on the HIGH to LOW transition of the clock (I2). The outputs of the last seven stages are available for additional flexibility.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995 |
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Philips Semiconductors Product specification
24-stage frequency divider and oscillator |
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HEF4521B |
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MSI |
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COUNT CAPACITY |
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OUTPUT |
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COUNT CAPACITY |
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O |
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218 = 262 144 |
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18 |
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O19 |
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219 = 524 288 |
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O20 |
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220 = 1 048 576 |
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O21 |
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221 = 2 097 152 |
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O22 |
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222 = 4 194 304 |
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Fig.2 |
Pinning diagram. |
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O23 |
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223 = 8 388 608 |
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O24 |
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224 = 16 777 216 |
HEF4521BP(N): |
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16-lead DIL; plastic (SOT38-1) |
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HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) |
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HEF4521BT(D): |
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16-lead SO; plastic (SOT109-1) |
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( ): Package Designator North America |
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FUNCTIONAL TEST SEQUENCE |
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INPUTS |
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CONTROL |
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OUTPUTS |
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TERMINALS |
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REMARKS |
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MR |
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I2 |
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O2 |
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VSS’ |
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VDD’ |
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O18 to O24 |
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H |
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L |
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L |
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VDD |
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VSS |
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L |
counter is in three 8-stage sections |
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in parallel mode; I2 and O2 are |
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interconnected (O2 is now input); |
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counter is reset by MR |
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L |
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VDD |
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VSS |
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H |
255 pulses are clocked into I2, O2 |
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(the counter advances on the LOW |
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to HIGH transition) |
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L |
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L |
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L |
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VSS |
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VSS |
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H |
VSS’ is connected to VSS |
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L |
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H |
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L |
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VSS |
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VSS |
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the input I2 is made HIGH |
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L |
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H |
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L |
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VSS |
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VDD |
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H |
VDD’ is connected to VDD; O2 is |
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now made floating and becomes an |
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output; the device is now in the |
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224 mode |
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L |
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VSS |
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VDD |
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L |
counter ripples from an all HIGH |
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state to an all LOW state |
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A test function has been included for the reduction of the test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections by connecting VSS’ to VDD and VDD’ to VSS. Via I2 (connected to O2) 255 counts are loaded into each of the 8-stage sections in parallel. All flip-flops are now at a HIGH state.
The counter is now returned to the normal 24-stage in series configuration by connecting VSS’ to VSS and VDD’ to VDD. One more pulse is entered into input I2, which will cause the counter to ripple from an all HIGH state to an all LOW state.
January 1995 |
3 |
_
1995 January
4
Fig.3 Logic diagram; for schematic diagram of clock circuit see Fig.4.
oscillator and divider frequency stage-24
HEF4521B MSI
Semiconductors Philips
specification Product
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