Philips hef4517b DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF4517B
LSI

Dual 64-bit static shift register

Product specification
File under Integrated Circuits, IC04

January 1995

Philips Semiconductors Product specification

Dual 64-bit static shift register

DESCRIPTION

The HEF4517B consists of two identical, independent
64-bit static shift registers. Each register has separate
clock (CP), data input (D), parallel
input-enable/output-enable (PE/EO) and four 3-state
outputs of the 16th, 32nd, 48th and 64th bit positions
(O16to O64). Data at the D input is entered into the first bit
on the LOW to HIGH transition of the clock, regardless of
the state of PE/EO.

HEF4517B

LSI

When PE/
device is in the 64-bit serial mode.

When PE/EO is HIGH the outputs are disabled (high
impedance OFF-state), the 64-bit shift register is divided
into four 16-bit shift registers with D, O16, O32and O48as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.

EO is LOW the outputs are enabled and the

Fig.1 Functional diagram.

FAMILY DATA, I

See Family Specifications

January 1995 2

LIMITS category LSI

DD

Philips Semiconductors Product specification

Dual 64-bit static shift register

HEF4517B

LSI

Fig.2 Pinning diagram.

HEF4517BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4517BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4517BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America

PINNING

CP

, CP

A

PE/

EOA, PE/EO

D

, D

A

B

, O

O

16A

O

, O

16B

, O

O

64A

B

32A
32B
64B

, O
, O

B

48A
48B

clock inputs
parallel input-enable/output-enable inputs
data inputs
3-state outputs/inputs
3-state outputs/inputs
3-state outputs

January 1995 3