Philips HEF4516BPB, HEF4516BP, HEF4516BDB, HEF4516BD, HEF4516BU Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4516B

MSI

Binary up/down counter

Product specification

 

January 1995

File under Integrated Circuits, IC04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Philips Semiconductors

Product specification

 

 

Binary up/down counter

HEF4516B

MSI

DESCRIPTION

The HEF4516B is an edge-triggered synchronous up/down 4-bit binary counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count

output (TC), and an overriding asynchronous master reset input (MR).

Fig.1 Functional diagram.

Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR which must be LOW. When PL and CE are LOW, the counter changes on the LOW to HIGH transition of CP.

Input UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O0 and O3 are HIGH and CE is LOW. When counting down, TC is LOW when O0 to O3 and

CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions.

Fig.2 Pinning diagram.

HEF4516BP(N): 16-lead DIL; plastic (SOT38-1)

HEF4516BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)

HEF4516BT(D): 16-lead SO; plastic (SOT109-1)

( ): Package Designator North America

PINNING

 

 

PL

parallel load input (active HIGH)

 

P0 to P3

parallel inputs

 

 

 

 

 

count enable input (active LOW)

 

CE

 

 

 

 

CP

clock pulse input (LOW to HIGH,

 

 

 

 

 

 

edge triggered)

 

 

 

 

 

up/down count control input

 

UP/DN

 

 

MR

master reset input

 

 

terminal count output (active LOW)

 

TC

 

 

O0 to O3

parallel outputs

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

Philips HEF4516BPB, HEF4516BP, HEF4516BDB, HEF4516BD, HEF4516BU Datasheet

Philips Semiconductors

Product specification

 

 

Binary up/down counter

HEF4516B

MSI

Fig.3 Logic diagram (continued in Fig.4).

January 1995

3

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