Philips HEF4040BU, HEF4040BT, HEF4040BPB, HEF4040BP, HEF4040BDB Datasheet
...
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4040B
MSI
12-stage binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
12-stage binary counter
HEF4040B
MSI
DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0to O11).
The counter advances on the HIGH to LOW transition of
CP. A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop. Schmitt-trigger action in the clock
input makes the circuit highly tolerant to slower clock rise
and fall times.
Fig.1 Functional diagram.
HEF4040BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4040BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4040BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4040B are:
• Frequency dividing circuits
• Time delay circuits
• Control counters
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
CP clock input (HIGH to LOW edge-triggered)
MR master reset input (active HIGH)
O
0
to O
11
parallel outputs
Loading...