Philips HEF40374BU, HEF40374BT, HEF40374BPB, HEF40374BP, HEF40374BDB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF40374B MSI

Octal D-type flip-flop with 3-state outputs

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Octal D-type flip-flop with 3-state outputs

HEF40374B

MSI

DESCRIPTION

The HEF40374B is an octal D-type flip-flop with 3-state buffered outputs with a common clock input (CP). The device is used primarily as an 8-bit positive edge-triggered storage register for interfacing with a 3-state bus. Data on the D-inputs is transferred to storage during the LOW-to-HIGH transition of the clock (CP) input. The 3-state output buffers are controlled by an active LOW output enable input (EO). A HIGH on EO forces the eight outputs to a high impedance OFF-state. When EO is LOW, the data in the register appears at the outputs.

Fig.1 Functional diagram.

The output stages have high current output capability suitable for driving highly capacitive loads.

The device features hysteresis on the CP input to improve noise rejection.

Schmitt-trigger action in the E input makes the circuit highly tolerant to slower input rise and fall times.

The HEF40374B is pin and functionally compatible with the TTL ‘374’ device.

Supply voltage range: 3 to 15 V.

Fig.2 Pinning diagram.

HEF40374BP(N): 20-lead DIL; plastic (SOT146-1)

HEF40374BD(F): 20-lead DIL; ceramic (cerdip) (SOT152)

HEF40374BT(D): 20-lead SO; plastic (SOT163-1)

( ): Package Designator North America

PINNING
	D0 to D7		data inputs
	CP		clock input
			output enable input (active LOW)
	EO
	O0 to O7		3-state buffered outputs

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

Philips Semiconductors	Product specification

Octal D-type flip-flop with 3-state outputs

HEF40374B

MSI

Fig.3 Logic diagram.

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January 1995

3