Philips hef4035b DATASHEETS

INTEGRATED CIRCUITS
DATA SH EET
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4035B MSI
4-bit universal shift register
Product specification File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
4-bit universal shift register

DESCRIPTION

The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR). Each register is of a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from P
to P3 on the LOW to HIGH transition of CP.
0
HEF4035B
MSI
When PE is LOW, data is shifted into the first register position from J and shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J andK. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and K = HIGH the first stage is in the hold mode.
The outputs (O0 to O3) are either inverting or non-inverting, depending on T/C state. With T/C HIGH, O0 to O3 are non-inverting (active HIGH) and when T/C is LOW, O0 to O3 are inverting (active LOW).
A HIGH on MR resets all four bit positions (O0to O3= LOW if T/C = HIGH, O0to O3= HIGH if T/C = LOW) independent of all other input conditions.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
K and all the data in the register is
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
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January 1995 3
Philips Semiconductors Product specification
4-bit universal shift register
Fig.2 Logic diagram.
HEF4035B
MSI
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