HEF4029BU
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4029B
MSI
Synchronous up/down counter,
binary/decade counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down
4-bit binary/BCD decade counter with a clock input (CP),
an active LOW count enable input (CE), an up/down
control input (UP/DN), a binary/decade control input
(BIN/DEC), an overriding asynchronous active HIGH
parallel load input (PL), four parallel data inputs (P
0
to P
3
),
four parallel buffered outputs (O
0
to O
3
) and an active
LOW terminal count output (TC).
Information on P
0
to P
3
is asynchronously loaded into the
counter while PL is HIGH, independent of CP.
The counter is advanced one count on the LOW to HIGH
transition of CP when CE and PL are LOW. TheTC signal
is normally HIGH and goes LOW when the counter
reaches its maximum count in the UP mode, or the
minimum count in the DOWN mode provided CE is LOW.
Fig.1 Functional diagram. Fig.2 Pinning diagram.
HEF4029BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4029BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4029BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
PL parallel load input
P
0
to P
3
parallel data inputs
BIN/
DEC binary/decade control input
UP/
DN up/down control input
CE count enable input (active LOW)
CP clock input (LOW to HIGH, edge triggered)
O
0
to O
3
buffered parallel outputs
TC terminal count output (active LOW)
January 1995 3
Philips Semiconductors Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995 4
Philips Semiconductors Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995 5
Philips Semiconductors Product specification
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going clock pulse edge
PL BIN/DEC UP/DN CE CP MODE
H X X X X parallel load (P
n
→ O
n
)
L X X H X no change
L L L L count-down, decade
L L H L count-up, decade
L H L L count-down, binary
L H H L count-up, binary
Fig.5 State diagram; BIN/DEC = LOW.
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