INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4027B flip-flops
Dual JK flip-flop
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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Dual JK flip-flop
HEF4027B flip-flops
DESCRIPTION
The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs
(O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FUNCTION TABLES
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INPUTS |
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OUTPUTS |
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SD |
CD |
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CP |
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J |
K |
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O |
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O |
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H |
L |
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X |
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X |
X |
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H |
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L |
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L |
H |
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X |
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X |
X |
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L |
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H |
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H |
H |
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X |
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X |
X |
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H |
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H |
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INPUTS |
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OUTPUTS |
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SD |
CD |
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CP |
J |
K |
On + 1 |
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n + 1 |
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O |
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L |
L |
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L |
L |
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no change |
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L |
L |
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H |
L |
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H |
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L |
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L |
L |
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L |
H |
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L |
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H |
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L |
L |
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H |
H |
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On |
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O |
n |
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Notes
1.H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial
= positive-going transition
On + 1 = state after clock positive transition
PINNING
J,K |
synchronous inputs |
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CP |
clock input (L to H edge-triggered) |
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SD |
asynchronous set-direct input (active HIGH) |
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CD |
asynchronous clear-direct input (active HIGH) |
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O |
true output |
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complement output |
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O |
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HEF4027BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4027BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category FLIP-FLOPS
See Family Specifications
Fig.2 Pinning diagram.
January 1995 |
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