Philips HEF4024BDB, HEF4024BD, HEF4024BU, HEF4024BT, HEF4024BPB Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4024B
MSI

7-stage binary counter

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

7-stage binary counter

HEF4024B

MSI

DESCRIPTION

The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.

Fig.1 Functional diagram.

HEF4024BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4024BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4024BT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

PINNING

APPLICATION INFORMATION

Some examples of applications for the HEF4024B are:

• Frequency dividers

• Time delay circuits

FAMILY DATA, I

DD

LIMITS category MSI

See Family Specifications

CP clock input (HIGH to LOW triggered)
MR master reset input
O

0

to O

6

buffered parallel outputs