Philips HEF4024BDB, HEF4024BD, HEF4024BU, HEF4024BT, HEF4024BPB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4024B MSI

7-stage binary counter

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

7-stage binary counter

HEF4024B

MSI

DESCRIPTION

The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW

transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop.

Fig.1 Functional diagram.

PINNING
			clock input (HIGH to LOW triggered)
	CP
	MR		master reset input
	O0 to O6		buffered parallel outputs

APPLICATION INFORMATION

Some examples of applications for the HEF4024B are:

∙ Frequency dividers

∙ Time delay circuits

Fig.2 Pinning diagram.

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

HEF4024BP(N):	14-lead DIL; plastic
	(SOT27-1)
HEF4024BD(F):	14-lead DIL; ceramic (cerdip)
	(SOT73)
HEF4024BT(D):	14-lead SO; plastic
	(SOT108-1)

( ): Package Designator North America

January 1995

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