Philips HEF4020BU, HEF4020BT, HEF4020BPB, HEF4020BP, HEF4020BDB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4020B MSI
14-stage binary counter
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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14-stage binary counter
HEF4020B
MSI
DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at
VDD = 15 V).
Fig.1 Functional diagram.
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HEF4020BP(N): |
16-lead DIL; plastic |
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(SOT38-1) |
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HEF4020BD(F): |
16-lead DIL; ceramic (cerdip) |
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(SOT74) |
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HEF4020BT(D): |
16-lead SO; plastic |
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(SOT109-1) |
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( ): Package Designator North America |
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PINNING |
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Fig.2 Pinning diagram. |
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CP |
clock input (HIGH to LOW edge |
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triggered) |
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MR |
master reset input (active HIGH) |
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O0, O3 to O13 |
parallel outputs |
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FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995 |
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