Philips HEF40193BU, HEF40193BT, HEF40193BP, HEF40193BDB, HEF40193BD Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF40193B MSI

4-bit up/down binary counter

Product specification

 

January 1995

File under Integrated Circuits, IC04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Philips Semiconductors

Product specification

 

 

4-bit up/down binary counter

HEF40193B

MSI

DESCRIPTION

The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input

(CPU), a count-down clock input (CPD), an asynchronous

parallel load input (PL), four parallel data inputs (P0 to P3), an asynchronous master reset input (MR), four counter outputs (O0 to O3), an active LOW terminal count-up

(carry) output (TCU) and an active LOW terminal

count-down (borrow) output (TCD).

 

 

 

 

 

 

Fig.1 Functional diagram.

 

 

 

 

 

 

 

PINNING

 

 

 

 

 

 

parallel load input (active LOW)

 

PL

 

 

 

 

P0 to P3

parallel data inputs

 

CPU

count-up clock pulse input (LOW to HIGH,

 

 

 

 

 

 

edge-triggered)

 

CPD

count-down clock pulse input (LOW to

 

 

 

 

 

 

HIGH, edge-triggered)

 

MR

master reset input (asynchronous)

 

 

 

 

buffered terminal count-up (carry) output

 

TC

U

 

 

 

 

 

 

(active LOW)

 

 

buffered terminal count-down

 

 

TC

D

 

 

 

 

 

 

(borrow) output (active LOW)

 

O0 to O3

buffered counter outputs

The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct counting, both clock inputs cannot be LOW simultaneously. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘15’, the next HIGH to LOW transition of CPU will

cause TCU to go LOW. TCU will stay LOW until CPU goes

HIGH again. Likewise, output TCD will go LOW when the

circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on P0 to P3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop.

Fig.2 Pinning diagram.

HEF40193BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF40193BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF40193BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category MSI

See Family Specification

January 1995

2

Philips HEF40193BU, HEF40193BT, HEF40193BP, HEF40193BDB, HEF40193BD Datasheet

Philips Semiconductors

Product specification

 

 

4-bit up/down binary counter

HEF40193B

MSI

Fig.3 Logic diagram (continued on Fig.4).

January 1995

3

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