Philips HEF40193BU, HEF40193BT, HEF40193BP, HEF40193BDB, HEF40193BD Datasheet
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF40193B
MSI
4-bit up/down binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
4-bit up/down binary counter
HEF40193B
MSI
DESCRIPTION
The HEF40193B is a 4-bit synchronous up/down
binary counter. The counter has a count-up clock input
(CPU), a count-down clock input (CPD), an asynchronous
parallel load input (PL), four parallel data inputs (P0to P3),
an asynchronous master reset input (MR), four counter
outputs (O0to O3), an active LOW terminal count-up
(carry) output (TCU) and an active LOW terminal
count-down (borrow) output (TCD).
The counter outputs change state on the LOW to HIGH
transition of either clock input. However, for correct
counting, both clock inputs cannot be LOW
simultaneously. The outputs
TCUand TCDare normally
HIGH. When the circuit has reached the maximum count
state of ‘15’, the next HIGH to LOW transition of CPUwill
cause TCUto go LOW. TCUwill stay LOW until CPU goes
HIGH again. Likewise, output TCDwill go LOW when the
circuit is in the zero state and CPDgoes LOW. When PL is
LOW, the information on P0to P3is asynchronously
loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter
stages are of a static toggle type flip-flop.
Fig.1 Functional diagram.
HEF40193BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40193BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40193BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
PL parallel load input (active LOW)
P
0
to P
3
parallel data inputs
CP
U
count-up clock pulse input (LOW to HIGH,
edge-triggered)
CP
D
count-down clock pulse input (LOW to
HIGH, edge-triggered)
MR master reset input (asynchronous)
TC
U
buffered terminal count-up (carry) output
(active LOW)
TC
D
buffered terminal count-down
(borrow) output (active LOW)
O
0
to O3buffered counter outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specification
January 1995 3
Philips Semiconductors Product specification
4-bit up/down binary counter
HEF40193B
MSI
Fig.3 Logic diagram (continued on Fig.4).
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